Emacs 修改verilog模式缩进

我试图让verilog模式使用2个空格缩进所有内容，除了decls和always。这是我添加到.emacs中的内容：

;; `define are not indented                                                                                                                                                                                                                                                    
(setq       verilog-indent-level-directive 0)
;;  always, initial etc not indented                                                                                                                                                                                                                                           
(setq       verilog-indent-level-module    0)
;; logic declarations are not indented                                                                                                                                                                                                                                         
(setq       verilog-indent-level-declaration 0)
;;2 space indent                                                                                                                                                                                                                                                               
(setq       verilog-indent-level             2)
;; no indent on list and no indent when on multiple lines                                                                                                                                                                                                                      
(setq       verilog-indent-lists           nil)
(setq       verilog-cexp-indent              0)

这是测试模块上的结果

`ifndef MY_MODULE_SV
`define MY_MODULE_SV

module my_module #(                                                                                                                                                                                                                                                            
parameter MyPar1 = 16,                                                                                                                                                                                                                                                         
parameter MyPar2 = 32                                                                                                                                                                                                                                                          
                   ) (
                   input logic        clk,
                   input logic        reset,
//comment indented weirdly                                                                                                                                                                                                                                                               
                   output logic [3:0] result
                   );

logic [3:0]                           count;


always @(posedge clk) begin
  //comment indented ok
  if (reset) begin
    count  <= 0;
    result <= 0;
  end
  else begin
    result   <= count;
    count    <= count+1;
  end
end

endmodule; // my_module                                                                                                                                                                                                                                                        

`endif

我正在使用emacs 24.3.1

---

我不知道如何仅使用verilog模式提供的变量来调整，有什么建议吗？

这与您要求的布局不完全匹配，但我要做的是将

#（

位于模块关键字下方，并将端口列表的参数列表中的结束参数和开始参数拆分为单独的行。结果如下。我的所有缩进都是3个空格，但您可以根据需要进行调整：

module my_module 
   #(
     parameter MyPar1 = 16,
     parameter MyPar2 = 32
     )
   (
    input logic        clk,
    input logic        reset,
    //comment indented weirdly
    output logic [3:0] result
    );

   logic [3:0]         count;

   always @(posedge clk) begin
      //comment indented ok
      if (reset) begin
         count  <= 0;
         result <= 0;
      end
      else begin
         result   <= count;
         count    <= count+1;
      end
   end

endmodule; // my_module                                                                                                                                                                                                                                                        

---

你的.emacs里有什么？

module my_module 
   #(
     parameter MyPar1 = 16,
     parameter MyPar2 = 32
     )
   (
    input logic        clk,
    input logic        reset,
    //comment indented weirdly
    output logic [3:0] result
    );

   logic [3:0]         count;

   always @(posedge clk) begin
      //comment indented ok
      if (reset) begin
         count  <= 0;
         result <= 0;
      end
      else begin
         result   <= count;
         count    <= count+1;
      end
   end

endmodule; // my_module                                                                                                                                                                                                                                                        

(custom-set-variables
 '(verilog-align-ifelse t)
 '(verilog-auto-delete-trailing-whitespace t)
 '(verilog-auto-inst-param-value t)
 '(verilog-auto-inst-vector nil)
 '(verilog-auto-lineup (quote all))
 '(verilog-auto-newline nil)
 '(verilog-auto-save-policy nil)
 '(verilog-auto-template-warn-unused t)
 '(verilog-case-indent 3)
 '(verilog-cexp-indent 3)
 '(verilog-highlight-grouping-keywords t)
 '(verilog-highlight-modules t)
 '(verilog-indent-level 3)
 '(verilog-indent-level-behavioral 3)
 '(verilog-indent-level-declaration 3)
 '(verilog-indent-level-module 3)
 '(verilog-tab-to-comment t))