If statement 如何在VHDL测试台中使用if语句来断言报告严重性语句？
好的。所以我要说为什么我要问这个问题。我们被告知要开发一个系统，该系统可以计算出能够解析公式的系统：If statement 如何在VHDL测试台中使用if语句来断言报告严重性语句？,if-statement,testing,vhdl,simulation,assert,If Statement,Testing,Vhdl,Simulation,Assert,好的。所以我要说为什么我要问这个问题。我们被告知要开发一个系统，该系统可以计算出能够解析公式的系统： O您可以包含实际的错误消息。如果有人会抱怨结束。在语法方面，它或者需要上一行断言语句的更多可选部分（由保留字severity或report之一表示）、布尔运算符（用于断言语句条件的延续-这些外圆括号没有特殊意义，不需要）或断言语句结束分号。您好，对不起，我忘了包含错误消息！非常感谢-仍然习惯于在堆栈溢出上发布帖子。非常感谢您对整个语法的其他评论：） LIBRARY ieee; USE ieee.
O您可以包含实际的错误消息。如果有人会抱怨
结束LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY algorith_TB IS
END algorith_TB;
ARCHITECTURE behavior OF algorith_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT algorithm
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
C : IN std_logic_vector(15 downto 0);
D : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(31 downto 0);
clk : IN std_logic;
rst : IN std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(15 downto 0); --:= (others => '0');
signal B : std_logic_vector(15 downto 0); --:= (others => '0');
signal C : std_logic_vector(15 downto 0); --:= (others => '0');
signal D : std_logic_vector(15 downto 0); --:= (others => '0');
signal clk : std_logic; --:= '0';
signal rst : std_logic; --:= '0';
--Outputs
signal O : std_logic_vector(31 downto 0);
-- Delay Constants Definition
constant propagation_delay : integer := 2;
constant num_vectors : integer := 5;
-- Clock period definitions
constant clk_period : time := 120 ns;
type test_vector is record
A : STD_LOGIC_VECTOR(15 downto 0);
B : STD_LOGIC_VECTOR(15 downto 0);
C : STD_LOGIC_VECTOR(15 downto 0);
D : STD_LOGIC_VECTOR(15 downto 0);
O : STD_LOGIC_VECTOR(31 downto 0);
end record;
type test_vector_array is array
(natural range<>) of test_vector;
constant test_vectors : test_vector_array := (
-- A B C D O
(x"0001", x"0002", x"0003", x"0004", x"0000000A") ,
(x"AAAA", x"0202", x"4131", x"4123", x"00004340") ,
(x"0001", x"0003", x"0005", x"0007", x"0000000C") ,
(x"AAAA", x"0202", x"4131", x"4123", x"00004340") ,
(x"0001", x"0003", x"0005", x"0007", x"0000000C") );
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: algorithm PORT MAP (
A => A,
B => B,
C => C,
D => D,
O => O,
clk => clk,
rst => rst
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 500 ns;
rst <= '1'; -- initial reset
wait for clk_period;
rst <= '0';
wait for clk_period*10; -- warm up period
wait until falling_edge(clk); -- resynchronise with falling edge
for i in 0 to 4 loop -- cycle through test vectors
if (i < num_vectors) then
A <= test_vectors(i).A;
B <= test_vectors(i).B;
C <= test_vectors(i).C;
D <= test_vectors(i).D;
wait for clk_period;
end if; -- end input loop if
if (i > propagation_delay) then -- pause for 2
assert (O = test_vectors(i-propagation_delay).O)
report "Test vector " & integer'image(i-propagation_delay) &
" failed for input A = " & integer'image(to_integer(unsigned(a))) &
"and b = " & integer'image(to_integer(unsigned(b))) &
" and C = " & integer'image(to_integer(unsigned(c))) &
"and D = " & integer'image(to_integer(unsigned(d)))
severity error;
end if; -- end assert check if
end loop; -- end for loop
wait;
end process;
END;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 500 ns;
rst <= '1'; -- initial reset
wait for clk_period;
rst <= '0';
wait for clk_period*10; -- warm up period
wait until falling_edge(clk); -- resynchronise with falling edge
for i in 0 to 4 loop -- cycle through test vectors
if (i < num_vectors) then
A <= test_vectors(i).A;
B <= test_vectors(i).B;
C <= test_vectors(i).C;
D <= test_vectors(i).D;
wait for clk_period;
end if; -- end input loop if
if (i > propagation_delay) then -- pause for 2
assert (O = test_vectors(i-propagation_delay).O)
end if; -- end assert check if
if (i - propagation_delay < 0) then
report "Test vector " & integer'image(i) &
" failed for input A = " & integer'image(to_integer(unsigned(a))) &
"and b = " & integer'image(to_integer(unsigned(b))) &
" and C = " & integer'image(to_integer(unsigned(c))) &
"and D = " & integer'image(to_integer(unsigned(d)))
severity error;
else
report "Test vector " & integer'image(i-propagation_delay) &
" failed for input A = " & integer'image(to_integer(unsigned(a))) &
"and b = " & integer'image(to_integer(unsigned(b))) &
" and C = " & integer'image(to_integer(unsigned(c))) &
"and D = " & integer'image(to_integer(unsigned(d)))
severity error;
end if; -- end report if
end loop; -- end for loop
wait;
end process;
END;
end if; -- end assert check if