Module 可以从32个1位加法器构建32位加法器吗？

我应该通过创建32条赋值语句来完成下面的模块 这似乎不是正确的做法。我知道我得把沙发抬上去， 但是当使用客户机模块创建和测试yAdder时，我得到了1+1=40亿的错误信息。哈哈。我知道它应该做什么，我只是不知道如何在verilog中做

    module yAdder(z,cout,a,b,cin);
output [31:0] z;
output cout;
input[31:0] a, b;
input cin;
wire[31:0] in,out;
yAdder1 mine[31:0](z,out,a,b,in);

assign in[0] = cin;
assign in[1] = out[0];
assign in[2] = out[0];
assign in[3] = out[0];
assign in[4] = out[0];
assign in[5] = out[0];
assign in[6] = out[0];
assign in[7] = out[0];
assign in[8] = out[0];
assign in[9] = out[0];
assign in[10] = out[0];
assign in[11] = out[0];
assign in[12] = out[0];
assign in[13] = out[0];
assign in[14] = out[0];
assign in[15] = out[0];
assign in[16] = out[0];
assign in[17] = out[0];
assign in[18] = out[0];
assign in[19] = out[0];
assign in[20] = out[0];
assign in[21] = out[0];
assign in[22] = out[0];
assign in[23] = out[0];
assign in[24] = out[0];
assign in[25] = out[0];
assign in[26] = out[0];
assign in[27] = out[0];
assign in[28] = out[0];
assign in[29] = out[0];
assign in[30] = out[0];
assign in[31] = out[0];
assign cout = out[0];


endmodule

以及1位加法器模块

module yAdder1(z,cout,a,b,cin);
output z, cout;
input a, b, cin;

xor left_xor(tmp,a,b);
xor right_xor(z,cin,tmp);
and left_and(outL,a,b);
and right_and(outR,tmp,cin);
or my_or(cout,outR,outL);

endmodule

---

将

out[0]

分配给all

in

导线可能不是最好的主意。你要找的可能是这样的：

assign {cout,in} = {out,cin};

    assign in[0] = cin;
    assign in[1] = out[0];
    assign in[2] = out[1];
    assign in[3] = out[2];
    assign in[4] = out[3];
    assign in[5] = out[4];
    assign in[6] = out[5];
    assign in[7] = out[6];
    assign in[8] = out[7];
    assign in[9] = out[8];
    assign in[10] = out[9];
    assign in[11] = out[10];
    assign in[12] = out[11];
    assign in[13] = out[12];
    assign in[14] = out[13];
    assign in[15] = out[14];
    assign in[16] = out[15];
    assign in[17] = out[16];
    assign in[18] = out[17];
    assign in[19] = out[18];
    assign in[20] = out[19];
    assign in[21] = out[20];
    assign in[22] = out[21];
    assign in[23] = out[22];
    assign in[24] = out[23];
    assign in[25] = out[24];
    assign in[26] = out[25];
    assign in[27] = out[26];
    assign in[28] = out[27];
    assign in[29] = out[28];
    assign in[30] = out[29];
    assign in[31] = out[30];
    assign cout = out[31];

---

对于这个预备实验室，你应该想象一下32位加法器，就像我们在上一个实验室做的4位加法器一样，然后像这样连接进位/进位线：

assign {cout,in} = {out,cin};

    assign in[0] = cin;
    assign in[1] = out[0];
    assign in[2] = out[1];
    assign in[3] = out[2];
    assign in[4] = out[3];
    assign in[5] = out[4];
    assign in[6] = out[5];
    assign in[7] = out[6];
    assign in[8] = out[7];
    assign in[9] = out[8];
    assign in[10] = out[9];
    assign in[11] = out[10];
    assign in[12] = out[11];
    assign in[13] = out[12];
    assign in[14] = out[13];
    assign in[15] = out[14];
    assign in[16] = out[15];
    assign in[17] = out[16];
    assign in[18] = out[17];
    assign in[19] = out[18];
    assign in[20] = out[19];
    assign in[21] = out[20];
    assign in[22] = out[21];
    assign in[23] = out[22];
    assign in[24] = out[23];
    assign in[25] = out[24];
    assign in[26] = out[25];
    assign in[27] = out[26];
    assign in[28] = out[27];
    assign in[29] = out[28];
    assign in[30] = out[29];
    assign in[31] = out[30];
    assign cout = out[31];

---

那么这个concates不能用out，而用cin？