Syntax error 第5行遗传算法的用户定义包RNG中存在VHDL语法错误

Syntax error 第5行遗传算法的用户定义包RNG中存在VHDL语法错误,syntax-error,vhdl,genetic-algorithm,xilinx,Syntax Error,Vhdl,Genetic Algorithm,Xilinx,第5行应为包rng is。欢迎使用堆栈溢出。事实上,您的错误是显而易见的,但如果不是这样,那么说出错误消息的实际内容会很有帮助。提交一行而不是数不清的代码也很有帮助。在组装MCVE时,您可能已经发现了错误。此外,如果您按照更常规的方式缩进代码,您也会发现它。 Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Type arr i

第5行应为包rng is。

欢迎使用堆栈溢出。事实上,您的错误是显而易见的,但如果不是这样,那么说出错误消息的实际内容会很有帮助。提交一行而不是数不清的代码也很有帮助。在组装MCVE时,您可能已经发现了错误。此外,如果您按照更常规的方式缩进代码,您也会发现它。
Library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

Type arr is array (1 to mut_bits) of integer;

type chrom_matrix is array (1 to pop_size) of std_logic_vector(1 to n_comp);

type fitness_arr is array (1 to pop_size) of integer range 0 to 1000;

--type fitness_arr1 is array(1 to pop_size) of real;

type adj_matrix is array (1 to n_comp,1 to n_comp) of bit;


function evalfnc (signal chromosome: in std_logic_vector(1 to 8); signal cut_info:adj_matrix) return integer;

procedure randg (variable x,y,t:in integer range 0 to 1000; variable z: out integer);

procedure convert_bit(variable a:in integer;variable y:out std_logic_vector(8 downto 1));

end rng;

package body rng is

procedure randg (variable x,y,t:in integer range 0 to 1000; variable z: out integer) is

variable val, a:integer range 0 to 1000:= 0;

begin

if x>y then

a:= x-y;

else

a:= y-x;

end if;

if t > 3*a then

  val:= (t-a)/2;

  elsif t > a then

  val:= t-a;

    else

    val:= (x+y+t)/2;

    end if;

    z:= val;

    end randg;

    function evalfnc (signal chromosome: in std_logic_vector(1 to 8); signal cut_info:adj_matrix) return integer is

    variable fitness: integer range 0 to 500:= 0;

    variable cut_val: integer range 0 to 15:= 0;

    variable max_fit:integer range 0 to 360:=100;

    begin

     for i in 1 to n_comp loop

       for j in 1 to n_comp loop

        if cut_info(i,j)= ‘1’ then

                               cut_val:= cut_val +1;

             end if;

    end loop;

 end loop;

   fitness := max_fit - cut_val;

   return fitness;

   end evalfnc;


procedure convert_bit(variable a:in integer ; variable y:out std_logic_vector(8 downto 1)) is

variable no:std_logic_vector(8 downto 1):=”00000000”;

variable num: integer range 0 to 256;

begin

    num:= a;

if num <= 255 and num>= 128 then

no(8):=’1’;

num:=num - 128;

end if;

if num < 128 and num >= 64 then

     no(7):=’1’;

     num:=num - 64;

end if;

     if num < 64 and num >= 32 then

     no(6):=’1’;

     num:=num −32;

end if;

if num < 32 and num >= 16 then

     no(5):=’1’;

     num:=num - 16;

       end if;

        if num < 16 and num >= 8 then

       no(4):=’1’;

       num:=num - 8;

           end if;

           if num < 8 and num >= 4 then

        no(3):=’1’;

         num:=num - 4;

                end if;

                if num < 4 and num >= 2 then

           no(2):=’1’;

          num:=num - 2;

                end if;

                if num < 2 then

           no(1):=’1’;

           end if;

y:= no;

end convert_bit;

end rng;