System verilog 如何使用同一类intest的两个不同实例?
在我的一个测试中,我有以下运行阶段任务:System verilog 如何使用同一类intest的两个不同实例?,system-verilog,uvm,System Verilog,Uvm,在我的一个测试中,我有以下运行阶段任务: //run_phase task run_phase(uvm_phase phase); tx_big_sml_diff_sequence tx_seq_i; axi_config_reg_sequence axi_seq_i; phase.raise_objection(.obj(this)); for (int i = 2; i <= 9; i++) begin
//run_phase
task run_phase(uvm_phase phase);
tx_big_sml_diff_sequence tx_seq_i;
axi_config_reg_sequence axi_seq_i;
phase.raise_objection(.obj(this));
for (int i = 2; i <= 9; i++) begin
tx_seq_i = tx_big_sml_diff_sequence::type_id::create(.name("tx_seq_i"), .contxt(get_full_name()));
axi_seq_i = axi_config_reg_sequence::type_id::create(.name("axi_seq_i"), .contxt(get_full_name()));
axi_seq_i.transfers[0] = i;
axi_seq_i.addr = `TX_FE_LIN_INT_ADDR;
fork
begin
tx_seq_i.start(grb_env_i.tx_lin_int_agent_i.tx_lin_int_sequencer);
end
begin
axi_seq_i.start(grb_env_i.axi_agent_i.axi_sequencer);
end
join
end
phase.drop_objection(.obj(this));
super.run_phase(phase);
endtask // run_phase
//运行\u阶段
任务运行阶段(uvm阶段);
tx_big_sml_diff_sequence tx_seq_i;
axi_config_reg_序列axi_seq_i;
阶段。提出异议(.obj(this));
对于(int i=2;i您没有提供有关axi\u config\u reg\u序列实现的任何详细信息,因此我假设addr
变量自动负责在该特定地址配置寄存器。如果是这样,您可以再次实例化同一序列,然后在他使用了如下所示的相同的定序器:
tx_seq_i = tx_big_sml_diff_sequence::type_id::create(.name("tx_seq_i"), .contxt(get_full_name()));
axi_seq1_i = axi_config_reg_sequence::type_id::create(.name("axi_seq1_i"), .contxt(get_full_name()));
axi_seq2_i = axi_config_reg_sequence::type_id::create(.name("axi_seq2_i"), .contxt(get_full_name()));
axi_seq1_i.transfers[0] = i;
axi_seq1_i.addr = `TX_FE_LIN_INT_ADDR;
axi_seq2_i.transfers[0] = `SET_THIS_VARIABLE_AS_NEEDED;
axi_seq2_i.addr = `YOUR_OTHER_ADDRESS_GOES_HERE;
fork
begin
tx_seq_i.start(grb_env_i.tx_lin_int_agent_i.tx_lin_int_sequencer);
end
begin
axi_seq1_i.start(grb_env_i.axi_agent_i.axi_sequencer);
axi_seq2_i.start(grb_env_i.axi_agent_i.axi_sequencer);
end
join
需要更多关于axi_配置_reg_序列的详细信息来回答问题