Time 实时仿真Quartus II中的错误
我正在学习如何使用Quartus II上的时间模拟来查看电路中的实际延迟,并且发生了错误。这个错误说明我不尊重触发器的保持时间。在逻辑模拟中,电路工作正常。 向下可以看到代码:Time 实时仿真Quartus II中的错误,time,simulation,verilog,digital-logic,quartus,Time,Simulation,Verilog,Digital Logic,Quartus,我正在学习如何使用Quartus II上的时间模拟来查看电路中的实际延迟,并且发生了错误。这个错误说明我不尊重触发器的保持时间。在逻辑模拟中,电路工作正常。 向下可以看到代码: module AddTestParalellIf(clk,reset, sum, out); input clk, reset; output sum, out; reg [15:0] sum; reg out ; always @(posedge clk ) begin if (res
module AddTestParalellIf(clk,reset, sum, out);
input clk, reset;
output sum, out;
reg [15:0] sum;
reg out ;
always @(posedge clk ) begin
if (reset) begin
sum = 0;
out = 0;
end
else
if (sum == 16'b0000000010000010)
out = 1;
sum = sum + 1;
end
endmodule
错误是:
Time: 0 ps Iteration: 0 Instance: /AddTestParalellIf_vlg_vec_tst File: plataformadetestes.vt
# ** Error: c:/altera/13.0/modelsim_ase/win32aloem/../altera/verilog /src/cycloneii_atoms.v(5351): $hold( posedge clk &&& nosloadsclr:27871 ps, datain:27922 ps, 286 ps );
# Time: 27922 ps Iteration: 0 Instance: /AddTestParalellIf_vlg_vec_tst/i1/\sum[1]~reg0
# ERROR! Vector Mismatch for output port out :: @time = 1000000.000 ps
# Expected value = 0
# Real value = x
# ERROR! Vector Mismatch for output port sum[1] :: @time = 1000000.000 ps
# Expected value = 0000000000000000
# Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[2] :: @time = 1000000.000 ps
# Expected value = 0000000000000000
# Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[3] :: @time = 1000000.000 ps
# Expected value = 0000000000000000
# Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[4] :: @time = 1000000.000 ps
# Expected value = 0000000000000000
# Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[5] :: @time = 1000000.000 ps
# Expected value = 0000000000000000
# Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[6] :: @time = 1000000.000 ps
# Expected value = 0000000000000000
# Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[7] :: @time = 1000000.000 ps
# Expected value = 0000000000000000
# Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[8] :: @time = 1000000.000 ps
# Expected value = 0000000000000000
# Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[9] :: @time = 1000000.000 ps
# Expected value = 0000000000000000
# Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[10] :: @time = 1000000.000 ps
# Expected value = 0000000000000000
# Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[11] :: @time = 1000000.000 ps
# Expected value = 0000000000000000
# Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[12] :: @time = 1000000.000 ps
# Expected value = 0000000000000000
# Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[13] :: @time = 1000000.000 ps
# Expected value = 0000000000000000
# Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[14] :: @time = 1000000.000 ps
# Expected value = 0000000000000000
# Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[15] :: @time = 1000000.000 ps
# Expected value = 0000000000000000
# Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[0] :: @time = 1005000.000 ps
# Expected value = 0000000000000000
# Real value = xxxxxxxxxxxxxxx1
# 17 mismatched vectors : Simulation failed !
# ** Note: $finish : plataformadetestes.vt(463)
# Time: 10 us Iteration: 0 Instance: /AddTestParalellIf_vlg_vec_tst/tb_out
我正在quartus II web上使用model sim simulator尝试在
else
子句中的两个语句周围添加开始
结束。如果断言了reset
,您似乎同时清除和递增sum
。尝试在else
子句中的两个语句周围添加开始结束
。如果断言了reset
,则您似乎同时清除和递增sum