Types xxx的VHDL类型与xxx的类型不兼容_Types_Casting_Vhdl

Types xxx的VHDL类型与xxx的类型不兼容

types vhdl

Types xxx的VHDL类型与xxx的类型不兼容,types,casting,vhdl,Types,Casting,Vhdl,Ich有两种不同的类型： type signal_4bit_t is record signals_v : STD_ULOGIC_VECTOR (3 downto 0); end record; type signal_8bit_t is record signals_v : STD_ULOGIC_VECTOR (7 downto 0); end record; 我创建了两个数组： type Array_signal_4bit_t is array (

Ich有两种不同的类型：

type signal_4bit_t is
record
   signals_v      : STD_ULOGIC_VECTOR (3 downto 0);
end record;

 type signal_8bit_t is
record
   signals_v      : STD_ULOGIC_VECTOR (7 downto 0);
end record;

我创建了两个数组：

 type Array_signal_4bit_t   is array (0 to 2) of signal_4bit_t;
 type Array_signal_8bit_t   is array (0 to 2) of signal_8bit_t;

一个实体使用4位数组作为输入：

entity test_input is
    Port ( 
           hx_i      : in  Array_signal_4bit_t;
           lx_i      : in  Array_signal_4bit_t;
          );
end test;

另一个使用8位阵列作为输出：

entity test_ouput is
    Port ( 
           out_o      : out Array_signal_8bit_t
          );
end test;

对于两个组件之间的连接，我使用信号：

signal tets_out_to_test_in   : Array_signal_8bit_t;

实例化如下所示：

in: test_input 
    Port Map ( 
           hx_i  =>    tets_out_to_test_in(7 downto 4),
           lx_i  =>    tets_out_to_test_in(3 downto 0)
          );

out: test_out 
    Port Map ( 
           out_o  =>    tets_out_to_test_in
          );

signal test_out_to_test_in   : Array_signal_8bit_t(0 to 2);
signal test_in_lo            : Array_signal_4bit_t(0 to 2);
signal test_in_hi            : Array_signal_4bit_t(0 to 2);

out: test_out 
  Port Map ( 
    out_o  =>  test_out_to_test_in
  );

gen : for i in test_out_to_test_in'range generate
  test_in_lo(i)   <= test_out_to_test_in(i)(3 downto 0);
  test_in_hi(i)   <= test_out_to_test_in(i)(7 downto 4);
end generate;

in: test_input 
  Port Map ( 
    hx_i  =>    test_in_hi,
    lx_i  =>    test_in_lo
  );

现在我得到错误“hx的类型I与tets的类型I不兼容。我看到数组信号4bit与数组信号8bit不同，但是有没有一种“简单”的方法可以在不改变我的属性的情况下解决这个问题？或者我知道如何解决这个问题吗？

你的代码有两个问题：

您必须寻址记录的成员才能访问内部std_ulogic_向量

您必须循环遍历向量的每个索引

test\u out\u to\u test\u in

，将其分配给结果向量。这可以通过生成语句或进程（不太好的解决方案）或函数（很好的解决方案）来完成

信号：

signal test_out_to_test_in   : Array_signal_8bit_t;
signal test_in_lo            : Array_signal_4bit_t;
signal test_in_hi            : Array_signal_4bit_t;

实例：

out: test_out 
  Port Map ( 
    out_o  =>  test_out_to_test_in
  );

gen : for i in test_out_to_test_in'range generate
  test_in_lo(i).signals_v   <= test_out_to_test_in(i).signals_v(3 downto 0);
  test_in_hi(i).signals_v   <= test_out_to_test_in(i).signals_v(7 downto 4);
end generate;

in: test_input 
  Port Map ( 
    hx_i  =>    test_in_hi,
    lx_i  =>    test_in_lo
  );

在大多数情况下，让数组类型不受约束更为灵活：

type Array_signal_4bit_t is array (NATURAL range <>) of signal_4bit_t;
type Array_signal_8bit_t is array (NATURAL range <>) of signal_8bit_t;

如果您对更多向量操作函数和过程感兴趣，请查看此软件包：

创建一个最小、可验证且完整的示例：

library ieee;
use ieee.std_logic_1164.all;

package somepack is
    type signal_4bit_t is
    record
       signals_v      : std_ulogic_vector (3 downto 0);
    end record;

     type signal_8bit_t is
    record
       signals_v      : std_ulogic_vector (7 downto 0);
    end record;
    type array_signal_4bit_t   is array (0 to 2) of signal_4bit_t;
    type array_signal_8bit_t   is array (0 to 2) of signal_8bit_t;
end package;

use work.somepack.all;
entity test_input is
    port ( 
           hx_i      : in  array_signal_4bit_t;
           lx_i      : in  array_signal_4bit_t
         );
end test_input;

architecture foo of test_input is
begin
end architecture;

use work.somepack.all;
entity test_output is
    port ( 
           out_o      : out array_signal_8bit_t
         );
end test_output;

architecture foo of test_output is
begin
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use work.somepack.all;

entity sometestbench is
end entity;

architecture foo of sometestbench is
    signal tets_out_to_test_in: array_signal_8bit_t;
    component test_input is
        port (
            hx_i: in  array_signal_4bit_t;
            lx_i: in  array_signal_4bit_t
        );
    end component;
    component test_output is
        port (
           out_o      : out array_signal_8bit_t        
        );
    end component;    

    signal hx_i_high: array_signal_4bit_t;
    signal lx_i_low:  array_signal_4bit_t;

begin

    hx_i_high(0).signals_v <= tets_out_to_test_in(0).signals_v(7 downto 4);
    hx_i_high(1).signals_v <= tets_out_to_test_in(1).signals_v(7 downto 4);
    hx_i_high(2).signals_v <= tets_out_to_test_in(2).signals_v(7 downto 4);
    lx_i_low(0).signals_v  <= tets_out_to_test_in(0).signals_v(3 downto 0);
    lx_i_low(1).signals_v  <= tets_out_to_test_in(1).signals_v(3 downto 0);
    lx_i_low(2).signals_v  <= tets_out_to_test_in(2).signals_v(3 downto 0);                

label_in: test_input 
    port map ( 
          --  hx_i  =>    tets_out_to_test_in(7 downto 4),
          hx_i => hx_i_high,
          --lx_i  =>    tets_out_to_test_in(3 downto 0)
          lx_i => lx_i_low
    );


label_out: test_output 
    port map ( 
           out_o  =>    tets_out_to_test_in
          );    
end architecture;

我们可以将formal的复合类型的元素分别映射到端口关联列表中的实际元素。此表单应该符合合成条件。

您的代码片段不包含，还存在语法错误。首先，谢谢。我尝试了您的解决方案，似乎很管用。Sorray我对VHDL比较陌生。因此，您能接受吗告诉我如何使用子类型或创建函数？@GerdMüller又添加了两个关于子类型和函数使用的示例。感谢函数。我在代码中实现了它，它很有效！非常感谢你的提示。之后，当我有两个数组信号4bit作为输出时，我遇到了问题，我必须用数组信号8b连接它们它。我用你的提示解决了它，我使用了一个过程。你最简单的我不能用，因为数组的大小应该是动态的，并用泛型设置。

function to_4bit_hi(value : Array_signal_8bit_t) return Array_signal_4bit_t is
  variable Result : Array_signal_4bit_t;
begin
  for i in value'range loop
    Result(i) <= value(i)(7 downto 4);
  end loop;
  return Result;
end function;

signal test_out_to_test_in   : Array_signal_8bit_t(0 to 2);
signal test_in_lo            : Array_signal_4bit_t(0 to 2);
signal test_in_hi            : Array_signal_4bit_t(0 to 2);

out: test_out 
  Port Map ( 
    out_o  =>  test_out_to_test_in
  );

test_in_lo   <= to_4bit_lo(test_out_to_test_in);
test_in_hi   <= to_4bit_hi(test_out_to_test_in);

in: test_input 
  Port Map ( 
    hx_i  =>    test_in_hi,
    lx_i  =>    test_in_lo
  );

library ieee;
use ieee.std_logic_1164.all;

package somepack is
    type signal_4bit_t is
    record
       signals_v      : std_ulogic_vector (3 downto 0);
    end record;

     type signal_8bit_t is
    record
       signals_v      : std_ulogic_vector (7 downto 0);
    end record;
    type array_signal_4bit_t   is array (0 to 2) of signal_4bit_t;
    type array_signal_8bit_t   is array (0 to 2) of signal_8bit_t;
end package;

use work.somepack.all;
entity test_input is
    port ( 
           hx_i      : in  array_signal_4bit_t;
           lx_i      : in  array_signal_4bit_t
         );
end test_input;

architecture foo of test_input is
begin
end architecture;

use work.somepack.all;
entity test_output is
    port ( 
           out_o      : out array_signal_8bit_t
         );
end test_output;

architecture foo of test_output is
begin
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use work.somepack.all;

entity sometestbench is
end entity;

architecture foo of sometestbench is
    signal tets_out_to_test_in: array_signal_8bit_t;
    component test_input is
        port (
            hx_i: in  array_signal_4bit_t;
            lx_i: in  array_signal_4bit_t
        );
    end component;
    component test_output is
        port (
           out_o      : out array_signal_8bit_t        
        );
    end component;    

    signal hx_i_high: array_signal_4bit_t;
    signal lx_i_low:  array_signal_4bit_t;

begin

    hx_i_high(0).signals_v <= tets_out_to_test_in(0).signals_v(7 downto 4);
    hx_i_high(1).signals_v <= tets_out_to_test_in(1).signals_v(7 downto 4);
    hx_i_high(2).signals_v <= tets_out_to_test_in(2).signals_v(7 downto 4);
    lx_i_low(0).signals_v  <= tets_out_to_test_in(0).signals_v(3 downto 0);
    lx_i_low(1).signals_v  <= tets_out_to_test_in(1).signals_v(3 downto 0);
    lx_i_low(2).signals_v  <= tets_out_to_test_in(2).signals_v(3 downto 0);                

label_in: test_input 
    port map ( 
          --  hx_i  =>    tets_out_to_test_in(7 downto 4),
          hx_i => hx_i_high,
          --lx_i  =>    tets_out_to_test_in(3 downto 0)
          lx_i => lx_i_low
    );


label_out: test_output 
    port map ( 
           out_o  =>    tets_out_to_test_in
          );    
end architecture;

    hx_i_high <= array_signal_4bit_t'(
               0 => (signals_v => tets_out_to_test_in(0).signals_v(7 downto 4)),
               1 => (signals_v => tets_out_to_test_in(1).signals_v(7 downto 4)),
               2 => (signals_v => tets_out_to_test_in(2).signals_v(7 downto 4))
               );

    lx_i_low <= array_signal_4bit_t'(
               0 => (signals_v => tets_out_to_test_in(0).signals_v(3 downto 0)),
               1 => (signals_v => tets_out_to_test_in(1).signals_v(3 downto 0)),
               2 => (signals_v => tets_out_to_test_in(2).signals_v(3 downto 0))
               );

anonymous <= E;

architecture fie of sometestbench is
    signal tets_out_to_test_in: array_signal_8bit_t;
    component test_input is
        port (
            hx_i: in  array_signal_4bit_t;
            lx_i: in  array_signal_4bit_t
        );
    end component;
    component test_output is
        port (
           out_o      : out array_signal_8bit_t        
        );
    end component;    

    signal hx_i_high: array_signal_4bit_t;
    signal lx_i_low:  array_signal_4bit_t;

    procedure slice_array_signal_8bit (
            signal input:   in  array_signal_8bit_t; 
            signal low:     out array_signal_4bit_t;
            signal high:    out array_signal_4bit_t
    ) is
    begin
        for i in array_signal_4bit_t'range loop
            high(i).signals_v <= input(i).signals_v(7 downto 4);
            low(i).signals_v  <= input(i).signals_v(3 downto 0);
        end loop;
    end procedure;

begin

BREAKOUT: 
slice_array_signal_8bit ( tets_out_to_test_in, hx_i_high, lx_i_low);             

label_in: test_input 
    port map ( 
          hx_i => hx_i_high,
          lx_i => lx_i_low
    );


label_out: test_output 
    port map ( 
           out_o  =>    tets_out_to_test_in
          );    
end architecture;

architecture foe of sometestbench is
    signal tets_out_to_test_in: array_signal_8bit_t;
    component test_input is
        port (
            hx_i: in  array_signal_4bit_t;
            lx_i: in  array_signal_4bit_t
        );
    end component;
    component test_output is
        port (
           out_o      : out array_signal_8bit_t        
        );
    end component;    

    signal hx_i_high: array_signal_4bit_t;
    signal lx_i_low:  array_signal_4bit_t;

begin

BREAKOUT: 
    process (tets_out_to_test_in)
    begin
        for i in array_signal_4bit_t'range loop
            hx_i_high(i).signals_v <= tets_out_to_test_in(i).signals_v(7 downto 4);
            lx_i_low(i).signals_v  <= tets_out_to_test_in(i).signals_v(3 downto 0);
        end loop;
    end process;          

label_in: test_input 
    port map ( 
          hx_i => hx_i_high,
          lx_i => lx_i_low
    );


label_out: test_output 
    port map ( 
           out_o  =>    tets_out_to_test_in
          );    
end architecture;

architecture fum of sometestbench is
    signal tets_out_to_test_in: array_signal_8bit_t;
    component test_input is
        port (
            hx_i: in  array_signal_4bit_t;
            lx_i: in  array_signal_4bit_t
        );
    end component;
    component test_output is
        port (
           out_o      : out array_signal_8bit_t
        );
    end component;
begin

label_in: test_input
    port map (
          hx_i(0).signals_v => tets_out_to_test_in(0).signals_v(7 downto 4),
          hx_i(1).signals_v => tets_out_to_test_in(1).signals_v(7 downto 4),
          hx_i(2).signals_v => tets_out_to_test_in(2).signals_v(7 downto 4),
          lx_i(0).signals_v => tets_out_to_test_in(0).signals_v(3 downto 0),
          lx_i(1).signals_v => tets_out_to_test_in(1).signals_v(3 downto 0),
          lx_i(2).signals_v => tets_out_to_test_in(2).signals_v(3 downto 0)
    );

label_out: test_output
    port map (
           out_o  =>    tets_out_to_test_in
          );
end architecture;