Vivado 2016.1:经过合成,它正在删除有用的逻辑。Verilog
我目前正致力于构建一个软核处理器,在合成一个Verilog实现的RAM和其他顺序元素时遇到了麻烦。我决定单独处理处理器的每个部分,以了解发生了什么,恐怕还没有运气。我试图合成的电路主要做两件事:用时钟驱动的数据填充内存;内存充满数据后,一个标志将指示向外部处理器发送信号,外部处理器将发送另一个名为ready的信号,以便读取和存储内存内容 这些是模块: 顶部模块 其他模块: 即使模拟工作正常,合成也会发出一些警告信息: 警告信息 我希望我能理解为什么,因为所有的元素都被使用了Vivado 2016.1:经过合成,它正在删除有用的逻辑。Verilog,verilog,fpga,ram,synthesis,vivado,Verilog,Fpga,Ram,Synthesis,Vivado,我目前正致力于构建一个软核处理器,在合成一个Verilog实现的RAM和其他顺序元素时遇到了麻烦。我决定单独处理处理器的每个部分,以了解发生了什么,恐怕还没有运气。我试图合成的电路主要做两件事:用时钟驱动的数据填充内存;内存充满数据后,一个标志将指示向外部处理器发送信号,外部处理器将发送另一个名为ready的信号,以便读取和存储内存内容 这些是模块: 顶部模块 其他模块: 即使模拟工作正常,合成也会发出一些警告信息: 警告信息 我希望我能理解为什么,因为所有的元素都被使用了 因此,如果您能帮助我
因此,如果您能帮助我找出问题所在以及解决方法,我将不胜感激。提前感谢:D T.T为了防止合成器删除“未使用的”逻辑,我在声明要保留的变量之前使用了以下语句:
EXAMPLE:
(*dont_touch = "true"*) output reg [7:0] out;
(*dont_touch = "true"*) reg COUNT = 0;
......
多亏了那些费心解释我不太理解的东西的人。现在代码工作得很好。我使用了don_touch,修改了RAM上的一些代码,并决定制作一个不同的输出和顶层模块,以实现在FPGA上进行测试的更简单方法。基本上,fill_mem模块用数据(顾名思义)填充内存,然后由另一个模块读取内存,该模块被带到电路板上的一些LED上,在那里可以检查存储的字节。通过开关选择读取地址 顶部模块 实例化模块 用于从RAM读取数据的硬件 用于填充闸板的HW 杂项。 达拉姆本身
模块数据存储器(时钟、地址、wr_-da、mem_-write、mem_-read、re_-da);
参数大小=24;
参数A=5;
输入[A-1:0]地址;
输入时钟;
输入[31:0]wr_da;
输入mem_write;
输入mem_read;
输出[31:0]re_da;
(*ram_style=“auto”*)reg[31:0]MEM[0:SIZE-1];
分配re_da=(内存读取)?MEM[地址]:0;
始终@(负边缘时钟)
开始
如果((内存写入)和(!内存读取))
开始
MEM[address]你知道合成会产生硬件,所以如果你用一些恒定的数据填充内存,而不是从中读取数据,那么合成工具会对其进行优化。我真的不明白你想做什么,这不是HDL,这是软件按顺序思考。问题是我确实读取了数据。com___;out模块在内存填满后提取此信息,这用于FPGA功能测试。是的,它是连续的,因为它和时钟信号是同步的。这是针对处理器的,处理器按顺序工作(除非您使用流水线,我不使用流水线,但它们仍按顺序读取指令)。所以是的,我需要先填好。他们读取它的内容,因为一个内存不应该同时读写。内存在4个时钟周期内被填满。一旦fill_mem模块完成此任务,它将发出一个标志(实际上是一个输出),并将此信号发送到一些mux和com_out。现在,com_out能够提取由信号就绪(FPGA输入)控制的信息。我计划用微控制器提取这个信息来做一些其他的事情,这就是为什么我也需要它的顺序。但是,再一次,如果你认为我做的是错误的方式,请告诉我应该怎么做。这就是为什么我来到这里寻求帮助毕竟N.NFYY你得到了组合循环在<代码> COMSOUT 。另外,always@(ready)
将在模拟电路和合成电路之间造成功能不匹配。必须指定完整的灵敏度列表以避免不匹配,或使用始终@*
。锁存器和触发器应分配非阻塞(这相当于忽略编译警告并覆盖它,说“我知道我在做什么”。我知道。一旦我在FPGA中测试代码,我会发现我是否正确。这比删除逻辑要好,那样电路也不会工作。顺便问一下,为什么只批评?我的意思是,你可以帮我告诉我应该怎么做@dave。对我来说,说别人错了是没有任何意义的如果你不纠正他们xD我一直都是在没有人帮助的情况下独自学习这一切,现在,我试着打电话寻求帮助,这就是发生的事情xD Welp,生活有时是讽刺的。祝你过得愉快dave。我不确定答案,但我知道这不是问题的答案。如果你有一个较小的例子显示这种行为,那么我可能会处于更好的位置我的评论不是给你看的,而是给下一个看到相同错误信息并想知道如何修复的人看的。然后我想让他们知道这不是正确的答案。嗯,我理解你的观点,我是这样做的。FPGA测试成功的,我对代码做了一些修改,因为synthes“我没有正确地推断RAM。但是不要碰其他东西也很好。也许这不是每个项目的正确答案,但它解决了我的部分问题:)所以,保持开放的心态,因为你的话也有一定的道理。@dave”
module data_memory(address,wr_da,mem_write,mem_read,re_da);
parameter SIZE = 16;
input [31:0] address;
input [31:0] wr_da;
input mem_write;
input mem_read;
output [31:0] re_da;
reg [7:0] MEM [0:SIZE-1];
assign re_da = (mem_read == 1) ? {MEM[address],MEM[address+1],MEM[address+2],MEM[address+3]}:0 ;
always @ (wr_da, address)
begin
if (mem_write == 1)
begin
MEM[address] = wr_da[31:24];
MEM[address+1] = wr_da[23:16];
MEM[address+2] = wr_da[15:8];
MEM[address+3] = wr_da[7:0];
end
end
module mux(a,b,c,o);
parameter N = 32;
input [N-1:0] a;
input [N-1:0] b;
input c;
output reg [N-1:0] o = 0;
always @*
begin
o = 0;
case (c)
0: o = a;
1: o = b;
default: o = 0;
endcase
end
endmodule
module com_out(ready,flag,in,out,sent,response,address);
input ready;
input flag;
input [31:0] in;
output reg [7:0] out;
output reg sent;
output reg [31:0] address = 0;
output response;
reg SINT = 0;
reg COUNT = 0;
reg R = 0;
reg [15:0] SEND = 0;
wire [7:0] DATA [3:0];
assign DATA[0] = in[31:24];
assign DATA[1] = in[23:16];
assign DATA[2] = in[15:8];
assign DATA[3] = in[7:0];
assign response = (R == 1) ? 1:0;
always @ (ready)
begin
out = 0;
if (ready == 1)
begin
if ((flag==1) && (SINT==0))
begin
out = DATA[SEND];
R = 1;
SEND = SEND+1;
if (SEND==4)
begin
address = address + 4;
SEND = 0;
COUNT = COUNT + 1;
end
else
address = address;
end
else
out = 0;
end
else
R = 0;
if (COUNT == 4)
begin
sent = 1;
SINT = 1;
end
else
begin
sent = 0;
SINT = 0;
end
end
endmodule
module fill_mem (clock,flag,out,ad);
input clock;
output reg flag = 0;
output reg [31:0] out = 0;
output [31:0] ad ;
reg [31:0] COMP = 0;
reg [31:0] COND = 0;
assign ad = COND;
always @ (negedge clock)
begin
COMP = COMP + 4;
COND = COMP - 4;
case (COND)
0 : out = 32'hACDECACA;
4 : out = 32'hACAFECAD;
8: out = 32'hCAFEBEEF;
12: out = 32'hDEADCAFE;
default: out = 0;
endcase
if (COMP >= 20)
flag = 1;
else
flag = 0;
end
endmodule
[Synth 8-3332] Sequential element (FM1/out_reg[31]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[27]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[26]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[25]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[24]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[23]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[20]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[19]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[18]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[11]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[10]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[9]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[7]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[5]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[4]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[3]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[2]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[1]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[0]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/COND_reg[0]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[0][3]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[1][3]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[2][3]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[3][3]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[4][3]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[5][3]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[6][3]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[7][3]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[8][3]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[9][3]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[10][3]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[11][3]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[12][3]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[13][3]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[14][3]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[15][3]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/COMP_reg[0]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/COMP_reg[1]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/COND_reg[1]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[8]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[0][0]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[2][0]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[4][0]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[6][0]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[8][0]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[10][0]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[12][0]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[14][0]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (CM1/address_reg[0]) is unused and will be removed from module DATATEST.
EXAMPLE:
(*dont_touch = "true"*) output reg [7:0] out;
(*dont_touch = "true"*) reg COUNT = 0;
......
module RAM_LEDS( clk, sw, led,lr,lb);
input clk;
input [3:0] sw;
output [3:0] led;
output [3:0] lr;
output [0:0] lb;
wire FLAG;
wire [3:0] EXT;
wire WD;
wire [31:0] MR,MW;
wire [4:0] RESU, A/*,B*/,FAD,LAD,AD,TA;
wire [7:0] LO;
assign led = LO[3:0];
assign lr = LO[7:4];
assign lb[0] = FLAG;
assign EXT = sw;
fill_mem FM1(.a(A),.out(MW),.ad(FAD));
adder_oi #(5) A1(.p(A),.result(RESU));
not_gate NG1(.I(FLAG),.O(WD));
mux #(5) MUX1(.a(FAD),.b(LAD),.c(FLAG),.o(AD));
bus #(5) B1(.clk(clk),.I(RESU),.O(A));
data_memory DM1(.clock(clk),.address(AD),.wr_da(MW),.mem_write(WD),.mem_read(FLAG),.re_da(MR));
peripheral P1(.a(FAD),.flag(FLAG));
extend EX1(.I(EXT),.O(TA));
switching S1(.ai(TA),.data(MR),.leds(LO),.ao(LAD));
endmodule
module peripheral(a,flag);
parameter A = 5;
input [A-1:0] a;
output flag;
assign flag = (a == 20) ? 1:0;
assign flag = (a == 20) ? 1:0;
endmodule
module extend(I,O);
input [3:0] I;
output [4:0] O;
assign O = {1'b0,I};
endmodule
module switching(ai,data,leds,ao);
input [4:0] ai;
input [31:0] data;
output reg [7:0] leds;
output reg [4:0] ao;
wire [7:0] D [0:3];
assign D[0] = data[7:0];
assign D[1] = data[15:8];
assign D[2] = data[23:16];
assign D[3] = data[31:24];
always @*
begin
case (ai)
0,1,2,3: ao = 0;
4,5,6,7: ao = 4;
8,9,10,11: ao = 8;
12,13,14,15: ao = 12;
default: ao = 0;
endcase
leds = D[ai%4];
end
endmodule
module fill_mem (a,out,ad);
parameter A = 5;
input [A-1:0] a;
output [31:0] out;
output [A-1:0] ad;
(* dont_touch = "true" *) reg [31:0] O = 0;
(* dont_touch = "true" *) reg [A-1:0] AR = 0;
assign out = O;
assign ad = AR;
always @*
begin
case (a)
0: begin AR = 0; O = 32'h00000000;; end
4: begin AR = 4; O = 32'hFFF00F00; end
8: begin AR = 8; O = 32'h9669C33C; end
12: begin AR = 12; O = 32'hF173371F; end
16: begin AR = 16; O = 32'hFFFFFFFF; end
default: begin AR = 20; O = 0; end
endcase
end
endmodule
module bus(clk,I,O);
parameter N = 32;
input clk;
input [N-1:0] I;
output [N-1:0] O;
(* dont_touch = "true" *)reg [N-1:0] C = 0;
assign O = C;
always @(posedge clk)
begin
C = I;
end
endmodule
module adder_oi(p,result); //PC+4
parameter N =32;
input [N-1:0] p;
output [N-1:0] result;
assign result = p + 4;
endmodule
module mux(a,b,c,o);
parameter N = 32;
input [N-1:0] a;
input [N-1:0] b;
input c;
output reg [N-1:0] o = 0;
always @*
begin
o = 0;
case (c)
0: o = a;
1: o = b;
default: o = 0;
endcase
end
endmodule
module data_memory(clock,address,wr_da,mem_write,mem_read,re_da);
parameter SIZE = 24;
parameter A = 5;
input [A-1:0] address;
input clock;
input [31:0] wr_da;
input mem_write;
input mem_read;
output [31:0] re_da;
(* ram_style = "auto" *) reg [31:0] MEM [0:SIZE-1];
assign re_da = (mem_read) ? MEM[address]:0;
always @(negedge clock)
begin
if ((mem_write) &&(!mem_read))
begin
MEM[address] <= wr_da;
end
end
endmodule