Verilog 覆盖置换
是否可以使用局部变量的各种排列创建覆盖点？像下面这样Verilog 覆盖置换,verilog,system-verilog,uvm,Verilog,System Verilog,Uvm,是否可以使用局部变量的各种排列创建覆盖点？像下面这样 covergroup test1 with function sample(int i) ; type_option.comment = "Config"; int array1 [] = {0,1}; int array2 [] = {3,4,9}; int array3 [] = {5,6}; coverpoint i { bins bin1 [] = {array1,array2}; bins
covergroup test1 with function sample(int i) ;
type_option.comment = "Config";
int array1 [] = {0,1};
int array2 [] = {3,4,9};
int array3 [] = {5,6};
coverpoint i
{
bins bin1 [] = {array1,array2};
bins bin2 [] = {array2,array3};
}
endgroup
不能在covergroup中声明局部变量，也不能在bin集合中进行数组操作。你能做的最接近的就是
int array1 [] = {0,1};
int array2 [] = {3,4,9};
int array3 [] = {5,6};
int binset1[];
int binset2[];
covergroup test1 with function sample(int i) ;
type_option.comment = "Config";
coverpoint i
{
bins bin1 [] = binset1;
bins bin2 [] = binset2;
}
endgroup
...
binset1 = {array1,array2};
binset2 = {array3,array4};
test1 = new();
请注意，并非所有模拟器都支持在bin表达式中使用类成员（如
array1array2编译器版本=VCS H-2013.06-SP1-11 VCS构建日期=2014年11月13日20:55:33const