Verilog 虽然代码编译成功，但未获得输出
我正在尝试实现8位条件和加法器，代码在quartus 2中成功编译，但我得到的输出是xxxxxxxx。不知道怎么了。Verilog 虽然代码编译成功，但未获得输出,verilog,quartus,Verilog,Quartus,我正在尝试实现8位条件和加法器，代码在quartus 2中成功编译，但我得到的输出是xxxxxxxx。不知道怎么了。 //用于8位条件和加法器的模块 module csa1(a,b,cin,sum,cout); parameter W=8; **// Inputs declarations** input [W-1:0] a, b; // Two inputs a and b with a carry in cin input cin; **// Outputs declar
//用于8位条件和加法器的模块
module csa1(a,b,cin,sum,cout);
parameter W=8;
**// Inputs declarations**
input [W-1:0] a, b; // Two inputs a and b with a carry in cin
input cin;
**// Outputs declarations**
output reg [W-1:0] sum; // Sum and carry cout
output reg cout;
**// Intermediate wires**
wire s1_0, c2_0, s2_0, c3_0, s3_0, c4_0, s4_0, c5_0, s5_0, c6_0, s6_0,c7_0,s7_0, c8_0;
wire s1_1, c2_1, s2_1, c3_1, s3_1, c4_1, s4_1, c5_1, s5_1, c6_1, s6_1, c7_1,s7_1, c8_1;
**// Intermediate registers**
reg fcout;
reg s3_level_1_0, s3_level_1_1, s5_level_1_0, s5_level_1_1, s7_level_1_0,s7_level_1_1;
reg c4_level_1_0, c4_level_1_1, c6_level_1_0, c6_level_1_1, c8_level_1_0,c8_level_1_1;
reg c2_level_1;
reg c4_level_2;
reg s6_level_2_0, s6_level_2_1, s7_level_2_0, s7_level_2_1, c8_level_2_0,c8_level_2_1;
**// Level 0**
always @*
{fcout,{sum[0]}}=a[0] + b[0] + cin;
**// Conditional cells instantiation**
conditional_cell c1( a[1], b[1], s1_0, s1_1, c2_0, c2_1);
conditional_cell c2( a[2], b[2], s2_0, s2_1, c3_0, c3_1);
conditional_cell c3( a[3], b[3], s3_0, s3_1, c4_0, c4_1);
conditional_cell c4( a[4], b[4], s4_0, s4_1, c5_0, c5_1);
conditional_cell c5( a[5], b[5], s5_0, s5_1, c6_0, c6_1);
conditional_cell c6( a[6], b[6], s6_0, s6_1, c7_0, c7_1);
conditional_cell c7( a[7], b[7], s7_0, s7_1, c8_0, c8_1);
**// Level 1 muxes**
always @*
case(fcout) // For first mux
1'b0:{c2_level_1,sum[1]}={c2_0,s1_0};
1'b1:{c2_level_1,sum[1]}={c2_1,s1_1};
endcase
always @* // For 2nd mux
case(c3_0)
1'b0: {c4_level_1_0, s3_level_1_0}={c4_0, s3_0};
1'b1: {c4_level_1_0, s3_level_1_0}={c4_1, s3_1};
endcase
always @* // For 3rd mux
case(c3_1)
1'b0: {c4_level_1_1, s3_level_1_1}={c4_0, s3_0};
1'b1: {c4_level_1_1, s3_level_1_1}={c4_1, s3_1};
endcase
always @* // For 4th mux
case(c5_0)
1'b0: {c6_level_1_0, s5_level_1_0}={c6_0, s5_0};
1'b1: {c6_level_1_0, s5_level_1_0}={c6_1, s5_1};
endcase
always @* // For 5th mux
case(c5_1)
1'b0: {c6_level_1_1, s5_level_1_1}={c6_0, s5_0};
1'b1: {c6_level_1_1, s5_level_1_1}={c6_1, s5_1};
endcase
always @* // For 6th mux
case(c7_0)
1'b0: {c8_level_1_0, s7_level_1_0}={c8_0, s7_0};
1'b1: {c8_level_1_0, s7_level_1_0}={c8_1, s7_1};
endcase
always @* // For 7th mux
case(c7_1)
1'b0: {c8_level_1_1, s7_level_1_1}={c8_0, s7_0};
1'b1: {c8_level_1_1, s7_level_1_1}={c8_1, s7_1};
endcase
**// Level 2 muxes**
always @* // First mux of level2
case(c2_level_1)
1'b0: {c4_level_2, sum[3], sum[2]}={c4_level_1_0,s3_level_1_0, s2_0};
1'b1: {c4_level_2, sum[3], sum[2]}={c4_level_1_1,s3_level_1_1, s2_1};
endcase
always @* // 2nd mux of level2
case(c6_level_1_0)
1'b0: {c8_level_2_0, s7_level_2_0, s6_level_2_0}={c8_level_1_0, s7_level_1_0, s6_0};
1'b1: {c8_level_2_0, s7_level_2_0, s6_level_2_0}={c8_level_1_1, s7_level_1_1, s6_1};
endcase
always @* // 3rd mux of level2
case(c6_level_1_1)
1'b0: {c8_level_2_1, s7_level_2_1, s6_level_2_1}={c8_level_1_0, s7_level_1_0, s6_0};
1'b1: {c8_level_2_1, s7_level_2_1, s6_level_2_1}={c8_level_1_1, s7_level_1_1, s6_1};
endcase
**// Level 3 mux**
always @*
case(c4_level_2)
1'b0: {cout,sum[7:4]}={c8_level_2_0, s7_level_2_0,s6_level_2_0, s5_level_1_0, s4_0};
1'b1: {cout,sum[7:4]}={c8_level_2_1, s7_level_2_1,s6_level_2_1, s5_level_1_1, s4_1};
endcase
endmodule
// Module for conditional cell
module conditional_cell(a, b, s_0, s_1, c_0, c_1);
input a,b;
output s_0, c_0, s_1, c_1;
assign s_0=a^b; // sum with carry in 0
assign c_0=a&b; // carry with carry in 0
assign s_1=~s_0; // sum with carry in 1
assign c_1=a | b; // carry with carry in 1
endmodule
你有这种设计的测试台吗？你能解释一下你到底做了什么吗？
**//comment******//comment****