如何在Verilog中合成While循环？
我曾尝试设计Booth乘法器，它在所有编译器中运行良好，包括： Modelsim、Verilogger Extream、Aldec Active Hdl和Xilinx的Isim 我知道模拟和合成是两个不同的过程，只有少数Verilog结构具有不同的限制用于合成。但是我不知道当我的程序中的循环在Synopsys Synplify 9.6和Xilinx ise 14.2中不起作用时会发生什么 当我尝试合成Synopsys时，会说“循环迭代限制2000已超过”，而Xilinx的XST会说“如何在Verilog中合成While循环？,verilog,system-verilog,Verilog,System Verilog,我曾尝试设计Booth乘法器，它在所有编译器中运行良好，包括： Modelsim、Verilogger Extream、Aldec Active Hdl和Xilinx的Isim 我知道模拟和合成是两个不同的过程，只有少数Verilog结构具有不同的限制用于合成。但是我不知道当我的程序中的循环在Synopsys Synplify 9.6和Xilinx ise 14.2中不起作用时会发生什么 当我尝试合成Synopsys时，会说“循环迭代限制2000已超过”，而Xilinx的XST会说“此Xilin
此Xilinx应用程序内存不足或遇到内存冲突”/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////Author/Coder-Shrikant Vaishnav///////////////////////////////////////////////
/////////////////////////////////////////Design-Booth Algorithm Demonstration////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
module booth_synt(input wire [4:0]a,input wire [4:0]b,output reg signed[9:0] g);
reg signed[10:0]c;// One extra bit for sign bit.....I mean 11th bit.
//We used Signed Reg bcoz ASR fill vacant bit with MSB and then shift other for unsigned reg they fill it with zeros and then shift..
reg[4:0]d;
reg [4:0]e;
reg [2:0]count1;
reg [2:0]count2;
reg [2:0]count3;
reg [2:0]count4;
//Always start whenever any changes happens
always@(a,b)
begin :close
//If's for sign bit check...
//Then 2's Complement...
count1=3'b000; //Initialize Counter
count2=3'b000;
count3=3'b000;
count4=3'b000;
//For negative
if(a[4]==1'b1) //Internal checking
begin
if(a==5'b10000)
begin
g[9:0]=10'b0000000000;
end
else
begin
d=~{1'b0,a[3],a[2],a[1],a[0]}; //we place 1'b0 because its inversion is 1
d=d+5'b00001; //2's Complement we use additional register d for data holding.....bcoz wire not hold data
if(d[4]==1'b0)//This "if" is used bcoz if due to calculation if accidently d[5]==1'b0 then this changs sign bit and thus ans
begin
d[4]=1'b1;
end
c[5:1]=d;
end
end
if(b[4]==1'b1)
begin
if(b==5'b10000)
begin
g[9:0]=10'b0000000000;
disable close;
end
else
begin
e=~{1'b0,b[3],b[2],b[1],b[0]}; //we place 1'b0 because its inversion is 1
e=e+5'b00001;
if(e[4]==1'b0)//This "if" is used bcoz if due to calculation if accidently e[4]==1'b0 then this changs sign bit and thus ans
begin
e[4]=1'b1;
end
end
end
//For positive
if(b[4]==1'b0)
begin
e[4:0]=b[4:0];
end
if(a[4]==1'b0)
begin
c[1]=a[0];
c[2]=a[1]; //"a" is multiplier while "b" is multiplicand...
c[3]=a[2];
c[4]=a[3];
c[5]=a[4];
end
//Initialization of Output ........
c[0]=1'b0;
//All MSB's are Initially set to Zeros
c[6]=1'b0;
c[7]=1'b0;
c[8]=1'b0;
c[9]=1'b0;
c[10]=1'b0;
//Four Different Conditions Checking......
case({c[1],c[0]})
2'b00:begin //Case 1
while(count1<3'b101) **<-------"Error Generated Here due to this while loop"**
begin
if({c[1],c[0]}==2'b10) //cond1 for 10
begin
c[10:6]=(c[10:6]-e[4:0]);
c=c>>>1;
count1=count1+1'b1;
if(count1==3'b101)// Counter value check
begin
if(c[10]==1)
begin
c=~{1'b0,c[9],c[8],c[7],c[6],c[5],c[4],c[3],c[2],c[1],c[0]};//we place 1'b0 because its inversion is 1
c=c+10'b0000000010;
c[10]=1'b1; //Again giving 1 for surity
g[9:0]=c[10:1];
end
if(c[10]==0)
begin
c[10]=1'b0;
g[9:0]=c[10:1];
end
end //end if==4
end
if(({c[1],c[0]}==2'b00) || ({c[1],c[0]}==2'b11)) //cond 2 in it we describe both 00 and11.........Arithemetic Right Shift operation
begin
c=c>>>1;
count1=count1+1'b1;
if(count1==3'b101) // Counter value check
begin
if(c[10]==1)
begin
c=~{1'b0,c[9],c[8],c[7],c[6],c[5],c[4],c[3],c[2],c[1],c[0]};//we place 1'b0 because its inversion is 1
c=c+10'b0000000010;
c[10]=1'b1; //Again giving 1 for surity
g[9:0]=c[10:1];
end
if(c[10]==0)
begin
c[10]=1'b0;
g[9:0]=c[10:1];
end
end
end
if({c[1],c[0]}==2'b01) //cond3 for 01
begin
c[10:6]=(c[10:6]+e[4:0]);
c=c>>>1;
count1=count1+1'b1;
if(count1==3'b101) // Counter value check
begin
if(c[10]==1)
begin
c=~{1'b0,c[9],c[8],c[7],c[6],c[5],c[4],c[3],c[2],c[1],c[0]};//we place 1'b0 because its inversion is 1
c=c+10'b0000000010;
c[10]=1'b1; //Again giving 1 for surity
g[9:0]=c[10:1];
end
if(c[10]==0)
begin
c[10]=1'b0;
g[9:0]=c[10:1];
end
end
end
end
end//while's end
//Case2
2'b11:begin
while(count2<3'b101) **<-------"Error Generated Here due to this while loop"**
begin
if({c[1],c[0]}==2'b10) //cond1 for 10
begin
c[10:6]=(c[10:6]-e[4:0]);
c=c>>>1;
count2=count2+1'b1;
if(count2==3'b101) // Counter value check
begin
if(c[10]==1)
begin
c=~{1'b0,c[9],c[8],c[7],c[6],c[5],c[4],c[3],c[2],c[1],c[0]};//we place 1'b0 because its inversion is 1
c=c+10'b0000000010;
c[10]=1'b1; //Again giving 1 for surity
g[9:0]=c[10:1];
end
if(c[10]==0)
begin
c[10]=1'b0;
g[9:0]=c[10:1];
end
end
end
if(({c[1],c[0]}==2'b00)||({c[1],c[0]}==2'b11))//cond 2 in it we describe both 00 and11.........Arithemetic Right Shift operation
begin
c=c>>>1;
count2=count2+1'b1;
if(count2==3'b101)// Counter value check
begin
if(c[10]==1)
begin
c=~{1'b0,c[9],c[8],c[7],c[6],c[5],c[4],c[3],c[2],c[1],c[0]};//we place 1'b0 because its inversion is 1
c=c+10'b0000000010;
c[10]=1'b1; //Again giving 1 for surity
g[9:0]=c[10:1];
end
if(c[10]==0)
begin
c[10]=1'b0;
g[9:0]=c[10:1];
end
end
end
if({c[1],c[0]}==2'b01) //cond3 for 01
begin
c[10:6]=(c[10:6]+e[4:0]);
c=c>>>1;
count2=count2+1'b1;
if(count2==3'b101)// Counter value check
begin
if(c[10]==1)
begin
c=~{1'b0,c[9],c[8],c[7],c[6],c[5],c[4],c[3],c[2],c[1],c[0]};//we place 1'b0 because its inversion is 1
c=c+10'b0000000010;
c[10]=1'b1; //Again giving 1 for surity
g[9:0]=c[10:1];
end
if(c[10]==0)
begin
c[10]=1'b0;
g[9:0]=c[10:1];
end
end
end
end
end //while's end
//Case 3
2'b10:begin
while(count3<3'b101) **<-------"Error Generated Here due to this while loop"**
begin
if({c[1],c[0]}==2'b10) //Cond1 for 10
begin
c[10:6]=(c[10:6]-e[4:0]);
c=c>>>1;
count3=count3+1'b1;
if(count3==3'b101)// Counter value check
begin
if(c[10]==1)
begin
c=~{1'b0,c[9],c[8],c[7],c[6],c[5],c[4],c[3],c[2],c[1],c[0]};//we place 1'b0 because its inversion is 1
c=c+10'b0000000010;
c[10]=1'b1; //Again giving 1 for surity
g[9:0]=c[10:1];
end
if(c[10]==0)
begin
c[10]=1'b0;
g[9:0]=c[10:1];
end
end
end
if(({c[1],c[0]}==2'b00)||({c[1],c[0]}==2'b11))//cond 2 in it we describe both 00 and11.........Arithemetic Right Shift operation
begin
c=c>>>1;
count3=count3+1'b1;
if(count3==3'b101)// Counter value check
begin
if(c[10]==1)
begin
c=~{1'b0,c[9],c[8],c[7],c[6],c[5],c[4],c[3],c[2],c[1],c[0]};//we place 1'b0 because its inversion is 1
c=c+10'b0000000010;
c[10]=1'b1; //Again giving 1 for surity
g[9:0]=c[10:1];
end
if(c[10]==0)
begin
c[10]=1'b0;
g[9:0]=c[10:1];
end
end
end
if({c[1],c[0]}==2'b01) //cond3 for 01
begin
c[10:6]=(c[10:6]+e[4:0]);
c=c>>>1;
count3=count3+1'd1;
if(count3==3'b101)// Counter value check
begin
if(c[10]==1)
begin
c=~{1'b0,c[9],c[8],c[7],c[6],c[5],c[4],c[3],c[2],c[1],c[0]};//we place 1'b0 because its inversion is 1
c=c+10'b0000000010;
c[10]=1'b1; //Again giving 1 for surity
g[9:0]=c[10:1];
end
if(c[10]==0)
begin
c[10]=1'b0;
g[9:0]=c[10:1];
end
end
end
end
end //while's end
//Case 4
2'b01:begin
while(count4<3'b101) **<-------"Error Generated Here due to this while loop"**
begin
if({c[1],c[0]}==2'b10) //cond1 for 10
begin
c[10:6]=(c[10:6]-e[4:0]);
c=c>>>1;
count4=count4+1'b1;
if(count4==3'b101)// Counter value check
begin
if(c[10]==1)
begin
c=~{1'b0,c[9],c[8],c[7],c[6],c[5],c[4],c[3],c[2],c[1],c[0]};//we place 1'b0 because its inversion is 1
c=c+10'b0000000010;
c[10]=1'b1; //Again giving 1 for surity
g[9:0]=c[10:1];
end
if(c[10]==0)
begin
c[10]=1'b0;
g[9:0]=c[10:1];
end
end
end
if(({c[1],c[0]}==2'b00)||({c[1],c[0]}==2'b11))//cond 2 in it we describe both 00 and11.........Arithemetic Right Shift operation
begin
c=c>>>1;
count4=count4+1'b1;
if(count4==3'b101)// Counter value check
begin
if(c[10]==1)
begin
c=~{1'b0,c[9],c[8],c[7],c[6],c[5],c[4],c[3],c[2],c[1],c[0]};//we place 1'b0 because its inversion is 1
c=c+10'b0000000010;
c[10]=1'b1; //Again giving 1 for surity
g[9:0]=c[10:1];
end
if(c[10]==0)
begin
c[10]=1'b0;
g[9:0]=c[10:1];
end
end
end
if({c[1],c[0]}==2'b01) //cond3 for 01
begin
c[10:6]=(c[10:6]+e[4:0]);
c=c>>>1;
count4<=count4+1'b1;
if(count4==3'b101)
begin
if(c[10]==1)
begin
c=~{1'b0,c[9],c[8],c[7],c[6],c[5],c[4],c[3],c[2],c[1],c[0]};//we place 1'b0 because its inversion is 1
c=c+10'b0000000010;
c[10]=1'b1; //Again giving 1 for surity
g[9:0]=c[10:1];
end
if(c[10]==0)
begin
c[10]=1'b0;
g[9:0]=c[10:1];
end
end
end
end //while's end
end//01's end
endcase //case end
end //always end
endmodule