FIFO（先进先出）的verilog代码未显示正确的结果？

我想设计一个具有一定深度和宽度的FIFO。FIFO的Verilog代码在Vivado 2017.4中编写。代码能够读取输入数据，但它仅显示XX作为输出。FIFO的设计来源和测试台如下所示。帮我找到问题

module fifo #(parameter WIDTH=8, parameter DEPTH=8) (
    input wire [WIDTH-1:0] data_in,
    output reg [WIDTH-1:0] data_out,
        output reg data_valid,
        input wire reset,
    input wire clk
    );
        function integer clog2(input reg [32-1:0] value); 
        begin 
            value = value-1;
            for (clog2=0; value>0; clog2=clog2+1)
                value = value>>1;
        end 
    endfunction
        reg [WIDTH-1:0] data [DEPTH-1:0];
    reg [clog2(DEPTH)-1:0] write_pointer;
    reg [clog2(DEPTH)-1:0] read_pointer;
        always @(posedge clk) begin
        if (reset == 1'b0) begin
            write_pointer <= 0;
            read_pointer <= 1;
            data_valid <= 0;
        end else begin
            if (write_pointer == DEPTH-1) write_pointer <= 0;
            else write_pointer <= write_pointer + 1;
                if (read_pointer == DEPTH-1) read_pointer <= 0;
            else read_pointer <= read_pointer + 1;
                data[write_pointer] <= data_in;
            data_out <= data[read_pointer];
        end
            if (read_pointer == 0) data_valid <= 1'b1;
    end
    endmodule

模块fifo#（参数宽度=8，参数深度=8）(
输入线[WIDTH-1:0]数据_in，
输出寄存器[WIDTH-1:0]数据输出，
输出注册表数据\u有效，
输入线复位，
输入线时钟
);
函数整数clog2（输入reg[32-1:0]值）；
开始
值=值-1；
用于（clog2=0；值>0；clog2=clog2+1）
值=值>>1；
结束
端功能
reg[WIDTH-1:0]数据[DEPTH-1:0]；
reg[clog2（深度）-1:0]写入指针；
reg[clog2（深度）-1:0]读取指针；
始终@（posedge clk）开始
如果（重置==1'b0）开始
在测试台代码中写入指针。时钟每5次改变一次：

// Create clock
always
    #5 clk = ~clk;

RTL中的重置使用此时钟的posedge：

always @(posedge clk) begin
    if (reset == 1'b0) begin
        write_pointer <= 0;
        read_pointer <= 1;
        data_valid <= 0;

始终@（posedge clk）开始
如果（重置==1'b0）开始
写入指针如果您将常量信号连接到
中的
数据，而不是尝试从文件中读取值，会发生什么情况？您需要更长时间的重置。您的模型没有看到在重置期间为#5（#1）的
posedge clk
。重置=0表示大约10次。非常感谢@serge，我差点就搞定了。你能把它作为答案吗。初始开始时钟=0；重置=0#10;         #1复位=1；我说得对吗？
always @(posedge clk) begin
    if (reset == 1'b0) begin
        write_pointer <= 0;
        read_pointer <= 1;
        data_valid <= 0;

initial begin
    clk = 0;
    reset = 1;
    #1 reset = 0;
    #1 reset = 1; // << one tick after the reset was asserted.
end

initial begin
    clk = 0;
    reset = 1;
    #1 reset = 0;
    #5 reset = 1; // << 5 tick after the reset was asserted. 

always @(posedge clk or reset) begin
    if (reset == 1'b0) begin
        write_pointer <= 0;
        read_pointer <= 1;
        data_valid <= 0;