Verilog Fifo块实现

我在verilog系统中编写了fifo 我尝试将一些数据推送到这个fifo（我写了一个tb），当我推送到数据时，fifo_wr_ptr、fifo_fre_空间、fifo_used_空间不会更新（只将数据写入mem[0]）

我会很高兴得到帮助（例如，为什么我的ptr不增加1）

非常感谢！ 这是我的模拟，显示了我的问题：

我附上了我的代码：

module fifo
#(parameter WIDTH = 32,   parameter DEPTH = 64 ) (   clk,   rst_l,   sw_rst,   fifo_din,   fifo_push_en,   fifo_pop_en,   fifo_dout,   fifo_o_full,   fifo_o_empty,   fifo_used_space,   fifo_free_space );




   function integer log2; //can use the $clog2() function
      input [31:0] value;
      reg [31:0]   value_tmp;
      begin      value_tmp = value;      for(log2=0; value_tmp>0; log2=log2+1)
       value_tmp=(value_tmp>>1);
      end    endfunction

localparam DEPTH_LOG2 = log2(DEPTH);

//interface  input clk; input rst_l; input sw_rst; input[WIDTH-1:0] fifo_din; input fifo_push_en; input fifo_pop_en; output logic[WIDTH-1:0] fifo_dout; output logic fifo_o_full; output logic fifo_o_empty; output logic[DEPTH_LOG2-1:0] fifo_used_space; output logic[DEPTH_LOG2-1:0] fifo_free_space; logic debug_flag; //internal logic logic[WIDTH-1:0] mem[DEPTH_LOG2-1:0]; logic[DEPTH_LOG2-1:0] fifo_rd_ptr,fifo_wr_ptr;

assign fifo_o_empty = (fifo_used_space==0); assign fifo_o_full  = (fifo_free_space==0);


always @ (posedge clk or negedge rst_l) begin    if(~rst_l) begin 
     fifo_free_space <= DEPTH;
     fifo_used_space <= 0;
     fifo_rd_ptr <= 0;
     fifo_wr_ptr <= 0;
     debug_flag <=0 ;

  end else if (~sw_rst) begin
     fifo_free_space <= DEPTH;
     fifo_used_space <= 0;
     fifo_rd_ptr <= 0;
     fifo_wr_ptr <= 0;
     debug_flag <= 0;

 end else if(fifo_push_en==1 && fifo_o_full==0 && fifo_pop_en==0) begin //the fifo isn't full and can perform the write trasaction (and no read transaction)
     fifo_used_space <= fifo_used_space + 1;
     fifo_free_space <= fifo_free_space - 1;
     mem[fifo_wr_ptr]<= fifo_din;
     debug_flag <= 1;
     if(fifo_wr_ptr == (DEPTH - 1)) 
        fifo_wr_ptr <= 0;
     else
        fifo_wr_ptr++;


     end else if (fifo_pop_en==1 && fifo_o_empty==0 && fifo_push_en==0) begin // the fifo isn't empty and can perform the read trasaction (and no write trasaction)
     fifo_used_space <= fifo_used_space - 1;
     fifo_free_space <= fifo_free_space + 1;
     fifo_dout       <= mem[fifo_rd_ptr];
     if(fifo_rd_ptr == (DEPTH - 1)) begin 
        fifo_rd_ptr  <= 0;
     end else begin 
        fifo_rd_ptr  <= fifo_rd_ptr + 1;
     end  end else begin

     fifo_rd_ptr     <= fifo_rd_ptr;
     //fifo_wr_ptr     <= fifo_wr_ptr;
     //fifo_dout       <= fifo_dout;
     //fifo_used_space <= fifo_used_space;
     fifo_free_space <= fifo_free_space;   end end

endmodule

---

撇开与指针递增相关的奇怪之处不谈，代码本身令人困惑，难以处理。粘贴参考FIFO模块，应该做的工作，这也应该帮助你掌握基本的编码风格

//----------------------------------------------------
// Module Name: fifo_sync.v
//----------------------------------------------------
// Description: generic sync FIFO module
//----------------------------------------------------

module fifo_sync #
(
    parameter FIFO_DATA_WIDTH = 'd32,
    parameter FIFO_PTR_WIDTH = 'd6
)
(
    //------------------------------------------------
    // Inputs
    //------------------------------------------------
    input                       clk,
    input                       rst_n,
    input                       wr_en,
    input [FIFO_DATA_WIDTH-1:0] wr_data,
    input                       rd_en,

    //------------------------------------------------
    // Outputs
    //------------------------------------------------
    output reg [FIFO_DATA_WIDTH-1:0] rd_data,
    output                           stat_full,
    output                           stat_empty,
    output     [ FIFO_PTR_WIDTH-1:0] stat_occupancy
);

    //------------------------------------------------
    // Local Parameters
    //------------------------------------------------
    localparam FIFO_DEPTH = 2**(FIFO_PTR_WIDTH-1);

    //------------------------------------------------
    // Internal Register(s)/Wire(s)/Integer(s)
    //------------------------------------------------
    reg [ FIFO_PTR_WIDTH-1:0] wr_ptr;
    reg [ FIFO_PTR_WIDTH-1:0] rd_ptr;
    reg [FIFO_DATA_WIDTH-1:0] fifo_array [FIFO_DEPTH-1:0];
    integer int_i;

    //------------------------------------------------
    // Write Pointer Logic
    //------------------------------------------------
    always @(posedge clk or negedge rst_n)
    begin: p_wr_ptr
        if (!rst_n)
            wr_ptr <= {FIFO_PTR_WIDTH{1'b0}};
        else if (wr_en & !stat_full)
            wr_ptr <= wr_ptr + 1'b1;
    end

    //------------------------------------------------
    // Read Pointer Logic
    //------------------------------------------------
    always @(posedge clk or negedge rst_n)
    begin: p_rd_ptr
        if (!rst_n)
            rd_ptr <= {FIFO_PTR_WIDTH{1'b0}};
        else if (rd_en & !stat_empty)
            rd_ptr <= rd_ptr + 1'b1;
    end

    //------------------------------------------------
    // Status Interface
    //------------------------------------------------

    // FIFO full status flag
    assign stat_full = (wr_ptr[FIFO_PTR_WIDTH-1] ^ rd_ptr[FIFO_PTR_WIDTH-1]) & (wr_ptr[FIFO_PTR_WIDTH-2:0] == rd_ptr[FIFO_PTR_WIDTH-2:0]);
    // FIFO empty status flag
    assign stat_empty = (wr_ptr == rd_ptr);
    // FIFO occupancy status
    assign stat_occupancy = wr_ptr - rd_ptr;

    //-----------------------------------------------
    // FIFO Write
    //-----------------------------------------------
    always @(posedge clk or negedge rst_n)
    begin: p_fifo_write
        if (!rst_n)
            for (int_i = 0; int_i < FIFO_DEPTH - 1; int_i = int_i + 1)
                fifo_array[int_i] <= {FIFO_DATA_WIDTH{1'b0}};
        else if (wr_en & !stat_full)
            fifo_array[wr_ptr] <= wr_data;
    end

    //-----------------------------------------------
    // FIFO Read
    //-----------------------------------------------
    always @(posedge clk or negedge rst_n)
    begin: p_fifo_read
        if (!rst_n)
            rd_data <= {FIFO_DATA_WIDTH{1'b0}};
        else if (rd_en & !stat_empty)
            rd_data <= fifo_array[rd_ptr];
    end

endmodule

//----------------------------------------------------
//模块名称：fifo_sync.v
//----------------------------------------------------
//描述：通用同步FIFO模块
//----------------------------------------------------
模块fifo_同步#
(
参数FIFO_数据_宽度='d32，
参数FIFO_PTR_WIDTH='d6
)
(
//------------------------------------------------
//投入
//------------------------------------------------
输入时钟，
输入rst\n，
输入wr_en，
输入[FIFO_数据_宽度-1:0]wr_数据，
输入rd_en，
//------------------------------------------------
//输出
//------------------------------------------------
输出reg[FIFO_数据_宽度-1:0]rd_数据，
输出stat_full，
输出stat_为空，
输出[FIFO\U PTR\U宽度-1:0]统计占用率
);
//------------------------------------------------
//局部参数
//------------------------------------------------
localparam FIFO_深度=2**（FIFO_PTR_宽度-1）；
//------------------------------------------------
//内部寄存器/导线/整数
//------------------------------------------------
reg[FIFO_PTR_WIDTH-1:0]wr_PTR；
reg[FIFO_PTR_WIDTH-1:0]rd_PTR；
reg[FIFO_数据_宽度-1:0]FIFO_阵列[FIFO_深度-1:0]；
整数int_i；
//------------------------------------------------
//写指针逻辑
//------------------------------------------------
始终@（posedge clk或negedge rst_n）
开始：p_wr_ptr
如果（！rst_n）
wr_ptr对我来说没有复杂的错误。@IdanRahamim fifo_wr_ptr在您的fifo模块中被注释掉了它是如何为您编译的？它应该抛出一个error@IdanRahamim我也不能编译它。vcs抛出15个错误。你需要用一个好的编译器来编译它。
//----------------------------------------------------
// Module Name: fifo_sync.v
//----------------------------------------------------
// Description: generic sync FIFO module
//----------------------------------------------------

module fifo_sync #
(
    parameter FIFO_DATA_WIDTH = 'd32,
    parameter FIFO_PTR_WIDTH = 'd6
)
(
    //------------------------------------------------
    // Inputs
    //------------------------------------------------
    input                       clk,
    input                       rst_n,
    input                       wr_en,
    input [FIFO_DATA_WIDTH-1:0] wr_data,
    input                       rd_en,

    //------------------------------------------------
    // Outputs
    //------------------------------------------------
    output reg [FIFO_DATA_WIDTH-1:0] rd_data,
    output                           stat_full,
    output                           stat_empty,
    output     [ FIFO_PTR_WIDTH-1:0] stat_occupancy
);

    //------------------------------------------------
    // Local Parameters
    //------------------------------------------------
    localparam FIFO_DEPTH = 2**(FIFO_PTR_WIDTH-1);

    //------------------------------------------------
    // Internal Register(s)/Wire(s)/Integer(s)
    //------------------------------------------------
    reg [ FIFO_PTR_WIDTH-1:0] wr_ptr;
    reg [ FIFO_PTR_WIDTH-1:0] rd_ptr;
    reg [FIFO_DATA_WIDTH-1:0] fifo_array [FIFO_DEPTH-1:0];
    integer int_i;

    //------------------------------------------------
    // Write Pointer Logic
    //------------------------------------------------
    always @(posedge clk or negedge rst_n)
    begin: p_wr_ptr
        if (!rst_n)
            wr_ptr <= {FIFO_PTR_WIDTH{1'b0}};
        else if (wr_en & !stat_full)
            wr_ptr <= wr_ptr + 1'b1;
    end

    //------------------------------------------------
    // Read Pointer Logic
    //------------------------------------------------
    always @(posedge clk or negedge rst_n)
    begin: p_rd_ptr
        if (!rst_n)
            rd_ptr <= {FIFO_PTR_WIDTH{1'b0}};
        else if (rd_en & !stat_empty)
            rd_ptr <= rd_ptr + 1'b1;
    end

    //------------------------------------------------
    // Status Interface
    //------------------------------------------------

    // FIFO full status flag
    assign stat_full = (wr_ptr[FIFO_PTR_WIDTH-1] ^ rd_ptr[FIFO_PTR_WIDTH-1]) & (wr_ptr[FIFO_PTR_WIDTH-2:0] == rd_ptr[FIFO_PTR_WIDTH-2:0]);
    // FIFO empty status flag
    assign stat_empty = (wr_ptr == rd_ptr);
    // FIFO occupancy status
    assign stat_occupancy = wr_ptr - rd_ptr;

    //-----------------------------------------------
    // FIFO Write
    //-----------------------------------------------
    always @(posedge clk or negedge rst_n)
    begin: p_fifo_write
        if (!rst_n)
            for (int_i = 0; int_i < FIFO_DEPTH - 1; int_i = int_i + 1)
                fifo_array[int_i] <= {FIFO_DATA_WIDTH{1'b0}};
        else if (wr_en & !stat_full)
            fifo_array[wr_ptr] <= wr_data;
    end

    //-----------------------------------------------
    // FIFO Read
    //-----------------------------------------------
    always @(posedge clk or negedge rst_n)
    begin: p_fifo_read
        if (!rst_n)
            rd_data <= {FIFO_DATA_WIDTH{1'b0}};
        else if (rd_en & !stat_empty)
            rd_data <= fifo_array[rd_ptr];
    end

endmodule