我如何修正警告；HDLCompiler:1007-memp中的元素索引7超出范围”；当我在Xilinx中使用Verilog描述硬件RAM时？

我对双端口RAM内存有以下硬件描述：

module MemoryRAM #(parameter  RAM_ADDR_BITS = 4, RAM_WIDTH = 8)
(CLK, RAMEnableLSB, RAMEnableMSB, WriteMemory,LoadData, Address, OutputRAMMEM);


input  RAMEnableLSB, RAMEnableMSB ,WriteMemory;
input CLK;


reg [RAM_WIDTH-1:0] RAM1 [(2**RAM_ADDR_BITS)-1:0];
reg [RAM_WIDTH-1:0] OutputData1 = 0,OutputData0 = 0;


input [RAM_ADDR_BITS-1:0] Address;
input [2*RAM_WIDTH-1:0] LoadData;
output [2*RAM_WIDTH -1:0] OutputRAMMEM;



always @ (posedge CLK)
begin
    if(RAMEnableMSB) begin
        if (WriteMemory) 
        begin
            RAM1[Address+1] <= LoadData[2*RAM_WIDTH-1:1*RAM_WIDTH];    //     Bit MSB
            OutputData1 <= LoadData[2*RAM_WIDTH-1:1*RAM_WIDTH];
        end
        else 
        begin
            OutputData1 <= RAM1[Address+1];           //     Bit MSB
        end
     end
     else
        OutputData1 <= 0;
end


always @ (posedge CLK)
begin
    if(RAMEnableLSB) begin
        if (WriteMemory) 
        begin
            RAM1[Address] <= LoadData[1*RAM_WIDTH-1:0*RAM_WIDTH];  //     Bit LSB
            OutputData0 <= LoadData[1*RAM_WIDTH-1:0*RAM_WIDTH];
        end
        else 
        begin
            OutputData0 <= RAM1[Address];           //     Bit LSB
        end
    end else
        OutputData0 <= 0;
end


assign OutputRAMMEM = {OutputData1,OutputData0};
endmodule

而且模拟不起作用！！！。重要的一点是，我正在使用ISim模拟器。如果我描述了单端口RAM的硬件，同样的警告也会出现

有人能告诉我如何解决此警告吗？

不确定“索引7”，但我注意到MSB的地址可能超出范围。

RAM1

的最大索引为15。MSB的最大地址为（15+1）

您可以向

RAM1

添加额外的索引，或者在地址溢出时将其包装回0。如果您扭曲它，则每个条目（如果MSB和LSB可以访问）都会被扭曲

二是扭曲地址。使用mod操作：

RAM1[(Address+1)%(2**RAM_ADDR_BITS)] <= LoadData[2*RAM_WIDTH-1:1*RAM_WIDTH];  

RAM1[(Address+1)%(2**RAM_ADDR_BITS)] <= LoadData[2*RAM_WIDTH-1:1*RAM_WIDTH];  

wire [RAM_ADDR_BITS:0] AddressMSB = Address+1;
...
RAM1[AddressMSB[RAM_ADDR_BITS-1:0]] <= LoadData[2*RAM_WIDTH-1:1*RAM_WIDTH];  //  Bit MSB
...