VHDL仿真中的未分配输出
我在ModelSim中用VHDL模拟代码时遇到了问题,代码的目的是对两个数字进行求和和和减法,以向量表示,并将结果存储在另外两个向量中。但是,当我开始模拟时,输出向量保持未赋值的值“U”。这段代码是我的教授写的,所以我相信里面没有错误,但我不知道如何让输出得到我想要的结果。代码及其测试台如下所示:VHDL仿真中的未分配输出,vhdl,modelsim,Vhdl,Modelsim,我在ModelSim中用VHDL模拟代码时遇到了问题,代码的目的是对两个数字进行求和和和减法,以向量表示,并将结果存储在另外两个向量中。但是,当我开始模拟时,输出向量保持未赋值的值“U”。这段代码是我的教授写的,所以我相信里面没有错误,但我不知道如何让输出得到我想要的结果。代码及其测试台如下所示: library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity addsub is
port (
\a\ : out std_logic_vector(31 downto 0);
\s\ : out std_logic_vector(31 downto 0);
\x\ : in std_logic_vector(31 downto 0);
\y\ : in std_logic_vector(31 downto 0)
);
end addsub;
architecture behavior of addsub is
component add_op_s
generic (
w_in1 : integer := 8;
w_in2 : integer := 8;
w_out : integer := 16
);
port (
I0 : in std_logic_vector(w_in1-1 downto 0);
I1 : in std_logic_vector(w_in2-1 downto 0);
O0 : out std_logic_vector(w_out-1 downto 0)
);
end component;
component sub_op_s
generic (
w_in1 : integer := 16;
w_in2 : integer := 16;
w_out : integer := 32
);
port (
I0 : in std_logic_vector(w_in1-1 downto 0);
I1 : in std_logic_vector(w_in2-1 downto 0);
O0 : out std_logic_vector(w_out-1 downto 0)
);
end component;
signal s5 : std_logic_vector(31 downto 0);
signal s3 : std_logic_vector(31 downto 0);
signal s4 : std_logic_vector(31 downto 0);
signal s2 : std_logic_vector(31 downto 0);
begin
\x_sub_op_s_y\: sub_op_s
generic map (
w_in1 => 32,
w_in2 => 32,
w_out => 32
)
port map (
I0 => s3,
I1 => s4,
O0 => s5
);
\x_add_op_s_y\: add_op_s
generic map (
w_in1 => 32,
w_in2 => 32,
w_out => 32
)
port map (
I0 => s3,
I1 => s4,
O0 => s2
);
s3 <= \x\;
s4 <= \y\;
\a\ <= s2;
\s\ <= s5;
end behavior;
IEEE库;
使用IEEE.std_logic_1164.all;
使用IEEE.std_logic_arith.all;
使用IEEE.std_logic_unsigned.all;
实体addsub是
港口(
\a \:输出标准逻辑向量(31向下至0);
\s \:输出标准逻辑向量(31向下至0);
\x \:标准逻辑向量中(31向下至0);
\y \:标准逻辑向量中(31向下至0)
);
end addsub;
addsub的体系结构行为
组件添加操作
一般的(
w_in1:整数:=8;
w_in2:整数:=8;
w_out:integer:=16
);
港口(
I0:标准逻辑向量(w_in1-1向下至0);
I1:标准逻辑向量(w_in2-1向下至0);
O0:out标准逻辑向量(w_out-1向下至0)
);
端部元件;
组件子组件
一般的(
w_in1:整数:=16;
w_in2:整数:=16;
w_out:integer:=32
);
港口(
I0:标准逻辑向量(w_in1-1向下至0);
I1:标准逻辑向量(w_in2-1向下至0);
O0:out标准逻辑向量(w_out-1向下至0)
);
端部元件;
信号s5:标准逻辑向量(31向下至0);
信号s3:标准逻辑向量(31向下至0);
信号s4:标准逻辑向量(31向下至0);
信号s2:标准逻辑向量(31向下至0);
开始
\x_sub_op_s_y \:sub_op_s
通用地图(
w_in1=>32,
w_in2=>32,
w_out=>32
)
港口地图(
I0=>s3,
I1=>s4,
O0=>s5
);
\x_添加_op_s_y \:添加_op_s
通用地图(
w_in1=>32,
w_in2=>32,
w_out=>32
)
港口地图(
I0=>s3,
I1=>s4,
O0=>s2
);
s3‘0’;
开始
uut:addsub
港口地图(
\a\=>\a\,
\s\=>\s\,
\x\=>\x\,,
\y\=>\y\
);
x_分布:过程
开始
等待10纳秒;
等待10纳秒;
\欢迎来到堆栈溢出。请花一点时间阅读,因为这将使您在使用此论坛时获得更好的回答率和体验。add_op_
和sub_op_
没有提供,因此如果这些都不包括在您的模拟中,它将不起作用。对于这样的代码调试,尽量减少设计,直到它变得非常简单,您可以发现错误;这将学习如何进行调试。欢迎使用堆栈溢出。请花一点时间阅读,因为这将使您在使用此论坛时获得更好的回答率和体验。add_op_
和sub_op_
没有提供,因此如果这些都不包括在您的模拟中,它将不起作用。对于这样的代码调试,尽量减少设计,直到它变得非常简单,您可以发现错误;这将学习您进行调试。
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity t_addsub is
end t_addsub;
architecture behavior of t_addsub is
component addsub
port (
\a\ : out std_logic_vector(31 downto 0);
\s\ : out std_logic_vector(31 downto 0);
\x\ : in std_logic_vector(31 downto 0);
\y\ : in std_logic_vector(31 downto 0)
);
end component;
signal \a\ : std_logic_vector(31 downto 0) := (others => '0');
signal \s\ : std_logic_vector(31 downto 0) := (others => '0');
signal \x\ : std_logic_vector(31 downto 0) := (others => '0');
signal \y\ : std_logic_vector(31 downto 0) := (others => '0');
begin
uut: addsub
port map (
\a\ => \a\,
\s\ => \s\,
\x\ => \x\,
\y\ => \y\
);
x_atribution: process
begin
wait for 10 ns;
wait for 10 ns;
\x\ <= conv_std_logic_vector(1,32);
wait for 10 ns;
\x\ <= conv_std_logic_vector(2,32);
wait for 10 ns;
\x\ <= conv_std_logic_vector(3,32);
wait for 10 ns;
\x\ <= conv_std_logic_vector('X', 32);
wait;
end process x_atribution;
y_atribution: process
begin
wait for 10 ns;
wait for 10 ns;
\y\ <= conv_std_logic_vector(3,32);
wait for 10 ns;
\y\ <= conv_std_logic_vector(2,32);
wait for 10 ns;
\y\ <= conv_std_logic_vector(1,32);
wait for 10 ns;
\y\ <= conv_std_logic_vector('X', 32);
wait;
end process y_atribution;
process
begin
wait for 10 ns;
wait on \s\;
assert \a\ = conv_std_logic_vector(4,32)
report "value different from the expected" severity error;
assert false report "end of test of \a\" severity note;
wait;
end process;
process
begin
wait for 10 ns;
wait on \s\;
assert \s\ = conv_std_logic_vector(-2,32)
report "value different from the expected" severity error;
wait on \s\;
assert \s\ = conv_std_logic_vector(0,32)
report "value different from the expected" severity error;
wait on \s\;
assert \s\ = conv_std_logic_vector(2,32)
report "value different from the expected" severity error;
assert false report "end of test of \s\" severity note;
wait;
end process;
process
begin
wait for 10 ns;
wait on \a\;
assert \a\ = conv_std_logic_vector(4,32)
report "value different from the expected" severity error;
wait for 12 ns;
assert \a\ = conv_std_logic_vector(4,32)
report "value different from the expected" severity error;
wait for 10 ns;
assert \a\ = conv_std_logic_vector(4,32)
report "value different from the expected" severity error;
assert false report "end of test of \a\" severity note;
wait;
end process;
process
begin
wait for 10 ns;
wait on \s\;
assert \s\ = conv_std_logic_vector(-2,32)
report "value different from the expected" severity error;
wait for 12 ns;
assert \s\ = conv_std_logic_vector(0,32)
report "value different from the expected" severity error;
wait for 10 ns;
assert \s\ = conv_std_logic_vector(2,32)
report "value different from the expected" severity error;
assert false report "end of test of \s\" severity note;
wait;
end process;
end behavior;