FIFO实现&VHDL
在将fifo代码实例化到顶层模块时,我又遇到了一个困难。我想从我的串行端口(接收子系统)存储一些数据集,比如“欢迎来到FPGA世界”,然后我想在按下FPGA板上的按钮或FIFO已满时检索它。我有我的fifo代码和串行通信代码写。想法是从键盘->接收子系统->FIFO->传输子系统->超级终端发送数据。我目前正在使用8位宽的fifo和28位深的fifo来存储一些小数据。在这方面,请帮助我如何实现它。我将来自接收器的字节保存在寄存器\u save中。FIFO实现&VHDL,vhdl,fpga,fifo,spartan,Vhdl,Fpga,Fifo,Spartan,在将fifo代码实例化到顶层模块时,我又遇到了一个困难。我想从我的串行端口(接收子系统)存储一些数据集,比如“欢迎来到FPGA世界”,然后我想在按下FPGA板上的按钮或FIFO已满时检索它。我有我的fifo代码和串行通信代码写。想法是从键盘->接收子系统->FIFO->传输子系统->超级终端发送数据。我目前正在使用8位宽的fifo和28位深的fifo来存储一些小数据。在这方面,请帮助我如何实现它。我将来自接收器的字节保存在寄存器\u save中。 inst_bit8_receive_单元:实体
inst_bit8_receive_单元:实体work.byte_receive_8N1
端口映射(ck=>ck,
重置=>重置,
缓冲区中的新字节=>缓冲区中的新字节,
字节从字节缓冲区读取=>字节从字节缓冲区读取,
接收缓冲区=>寄存器保存,
JA_2=>JA(2));
---------------------先进先出实例化-------------------------------
代替fifo接收单元:实体work.fifo
通用映射(B=>数据位,W=>fifo宽度)
端口映射(ck=>ck,
重置=>重置,
rd=>rd_rx,
wr=>wr_rx,
write_data=>num_received,
read_data=>num_received_fifo,
empty=>empty_rx,
满=>满_rx);
指令位8发送单元:实体工作。字节发送单元8N1
端口映射(ck=>ck,
重置=>重置,
发送字节准备就绪=>发送字节准备就绪,
发送字节完成=>发送字节完成,
发送缓冲区=>num\u发送,
JAOUT_0=>JAOUT);
proc_send5byte:进程(ck、reset、state_byte5、send_byte_done、num_send、state_button_0、num_received_fifo、rd_rx)
开始
如果重置='1',则
先进先出的原则是先进先出。你不必管理它
您将数据放在fifo的输入上
将写启用位设置为“1”
你等待一个时钟周期
将写启用位设置为“0”
然后数据被存储,您再次这样做以存储另一个值
当您想要读取所有数据时(Fifo满/您想要的任何情况)
您将读取启用位设置为“1”,每个时钟周期,您将收到一个数据。--接收字节并发送给fifo输入的过程,以及写入启用信号--------
--- process for recieving bytes and sent to fifo input with write enable signal------------
proc_recieving_byte : process (ck, reset, register_save, new_byte_in_buffer, full_rx, num_recieved, wr_rx)
begin
if reset = '1' then
byte_read_from_buffer <= '0';
else
if rising_edge(ck) then
if full_rx = '0' then
if new_byte_in_buffer = '1' and byte_read_from_buffer = '0' then
byte_read_from_buffer <= '1';
wr_rx <= '1';
num_recieved(7 downto 0 ) <= register_save( 7 downto 0);
else
wr_rx <= '0';
end if;
end if;
if new_byte_in_buffer = '0' then
byte_read_from_buffer <= '0';
wr_rx <= '0';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------------------------------------------
---- this process checks first button state and then transmission occurs from fifo untill empty------
proc_send5byte: process(ck, reset, state_byte5, send_byte_done, num_send, state_button_0, num_recieved_fifo, rd_rx)
begin
if reset = '1' THEN
state_byte5 <= idle;
send_byte_ready <='0';
num_send <= "00000000" ;
else
if rising_edge(ck) then
case state_byte5 is
when idle => ---- in this, if btn(0) is high i.e pressed then only state_byte5 will go to next state
if state_button_0 = transit_pressed then
state_byte5 <= byte;
end if;
-----===============================================================
when byte =>
if (not empty_rx = '1') then
if send_byte_ready ='0' and send_byte_done = '0' then ----here if condition is satified the send_byte_ready will be set
send_byte_ready <='1'; --------- shows next byte is ready
num_send <= num_recieved_fifo;
rd_rx <='1';
else
rd_rx <='0';
end if;
end if;
if send_byte_ready = '1' and send_byte_done = '1' then --- during load state send_byte will be resets
send_byte_ready <='0';
rd_rx <= '0';
state_byte5 <= idle; ----------- go back to idle
end if;
---===============================================================
when others =>
state_byte5 <= idle;
send_byte_ready <= '0';
rd_rx <= '0';
end case;
end if;
end if;
end process;
proc_receiving_byte:处理(ck、reset、寄存器保存、缓冲区中的新字节、完整接收、接收数量、wr_接收)
开始
如果重置='1',则
字节从缓冲区读取如果你有关于特定代码的特定问题,请提问,有人会非常乐意回答。但这不是一个代码编写服务。我明白你的话。但我需要帮助每次递增或追加收到的字节,直到fifo满为止。这一部分让我感到困惑,我是应该在每次保存字节时检查fifo深度,还是它会自己保存直到它满为止。这个问题完全不可理解。请阅读。很抱歉,您编辑的代码越来越多,无法澄清您的问题。请再次检查编辑的问题,我缺少字节。请看一下代码和链接。如果上升沿(ck),那么如果计数<计数最大值,那么wr\u rx,在这个例子中,我尝试将接收到的每个字节(num\u received)写入fifo。是否还应检查fifo是否已满。请小心,因为当计数>count\u max
时,它将返回到0,之后的时钟周期,它将在第一个if条件下重新输入,并尝试写入fifo,计数将增加。您应该使用启用信号来控制。在处理fifo时,强烈建议使用full\u fifo
和empty\u fifo
。请您解释一下使用full和empty信号。我试着这样做,如果计数--- process for recieving bytes and sent to fifo input with write enable signal------------
proc_recieving_byte : process (ck, reset, register_save, new_byte_in_buffer, full_rx, num_recieved, wr_rx)
begin
if reset = '1' then
byte_read_from_buffer <= '0';
else
if rising_edge(ck) then
if full_rx = '0' then
if new_byte_in_buffer = '1' and byte_read_from_buffer = '0' then
byte_read_from_buffer <= '1';
wr_rx <= '1';
num_recieved(7 downto 0 ) <= register_save( 7 downto 0);
else
wr_rx <= '0';
end if;
end if;
if new_byte_in_buffer = '0' then
byte_read_from_buffer <= '0';
wr_rx <= '0';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------------------------------------------
---- this process checks first button state and then transmission occurs from fifo untill empty------
proc_send5byte: process(ck, reset, state_byte5, send_byte_done, num_send, state_button_0, num_recieved_fifo, rd_rx)
begin
if reset = '1' THEN
state_byte5 <= idle;
send_byte_ready <='0';
num_send <= "00000000" ;
else
if rising_edge(ck) then
case state_byte5 is
when idle => ---- in this, if btn(0) is high i.e pressed then only state_byte5 will go to next state
if state_button_0 = transit_pressed then
state_byte5 <= byte;
end if;
-----===============================================================
when byte =>
if (not empty_rx = '1') then
if send_byte_ready ='0' and send_byte_done = '0' then ----here if condition is satified the send_byte_ready will be set
send_byte_ready <='1'; --------- shows next byte is ready
num_send <= num_recieved_fifo;
rd_rx <='1';
else
rd_rx <='0';
end if;
end if;
if send_byte_ready = '1' and send_byte_done = '1' then --- during load state send_byte will be resets
send_byte_ready <='0';
rd_rx <= '0';
state_byte5 <= idle; ----------- go back to idle
end if;
---===============================================================
when others =>
state_byte5 <= idle;
send_byte_ready <= '0';
rd_rx <= '0';
end case;
end if;
end if;
end process;