Vhdl 获取未定义的符号错误,即使变量是按语法定义的
我没有提到的所有其他变量都定义为整数,具有适当的范围,并且都是按语法定义的 但是我得到了一个“未定义符号”的错误,还有完整的_pwm1_1常数。Vhdl 获取未定义的符号错误,即使变量是按语法定义的,vhdl,Vhdl,我没有提到的所有其他变量都定义为整数,具有适当的范围,并且都是按语法定义的 但是我得到了一个“未定义符号”的错误,还有完整的_pwm1_1常数。 是否有人可以帮助我,并验证数组声明和实例化是否正确?在“架构”行和“开始”行之间写入类型和常量声明,例如: architecture beh of pwm is begin type lutable is array (1 to 64) of integer range 0 to 4000; -----------------------------
是否有人可以帮助我,并验证数组声明和实例化是否正确?在“架构”行和“开始”行之间写入类型和常量声明,例如:
architecture beh of pwm is
begin
type lutable is array (1 to 64) of integer range 0 to 4000;
-----------------------------------------------tables for FULL STEPPING.
constant full_pwm1_1: lutable := ( 3900,0,0,3900, 3900,0,0,3900, 3900,0,0,3900, 3900,0,0,3900,
3900,0,0,3900, 3900,0,0,3900, 3900,0,0,3900, 3900,0,0,3900,
3900,0,0,3900, 3900,0,0,3900, 3900,0,0,3900, 3900,0,0,3900,
3900,0,0,3900, 3900,0,0,3900, 3900,0,0,3900, 3900,0,0,3900);
variable ds1_1: integer range 0 to 4000; --Duty Cycle Variables for PWM1_1
variable c_full,c_half,c_quat,c_eigh,c_sixt: integer range 1 to 64;
process(gclk)
begin
case selectline is
when "001" => --------------------FULL STEPPING
if dir='1' then--------------------direction selection
ds1_1 := full_pwm1_1(c_full);
在“进程”和“开始”之间写入变量声明,例如
或将ds1_1等声明为信号,例如:
process(gclk)
variable ds1_1: integer range 0 to 4000; --Duty Cycle Variables for PWM1_1
variable c_full,c_half,c_quat,c_eigh,c_sixt: integer range 1 to 64;
begin
...
类型和常量声明必须在
体系结构
之后和开始
之前
此外,本节中不能有变量,它们必须是
过程中的普通变量
- 共享变量。。。必须是受保护的类型,而不是普通类型
mypack
这样的包中声明,您是否记得在启动架构之前“使用work.mypack.all”?
process(gclk)
variable ds1_1: integer range 0 to 4000; --Duty Cycle Variables for PWM1_1
variable c_full,c_half,c_quat,c_eigh,c_sixt: integer range 1 to 64;
begin
...
...
signal ds1_1: integer range 0 to 4000; --Duty Cycle Variables for PWM1_1
signal c_full,c_half,c_quat,c_eigh,c_sixt: integer range 1 to 64;
...
begin
...
process(gclk)
...