VHDL非法使用信号声明

以下是我的代码：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY work4 IS
PORT (  CS: IN STD_LOGIC;
        RD: IN STD_LOGIC;
        WR: IN STD_LOGIC;
        DATA : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
 END work4; 
ARCHITECTURE behav OF work4 IS BEGIN 

PROCESS(CS, RD,WR) 
SIGNAL T: STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN 
 IF CS'EVENT AND CS = '1' THEN 
    IF WR='1' AND RD='0' THEN DATA<=T;
    ELSE IF WR='0' AND RD='1' THEN T<=DATA;
    END IF;
END IF;
END IF; 
 END PROCESS; 
 END behav;

我知道我使用了错误的信号，但不知道哪里出了问题

---

有人能帮忙吗

过程声明部分中允许的过程声明项在IEEE Std 1076-2008 11.3过程声明第2段中定义：

 process_declarative_item ::=
        subprogram_declaration
      | subprogram_body
      | type_declaration
      | subtype_declaration
      | constant_declaration
      | variable_declaration
      | file_declaration
      | alias_declaration
      | attribute_declaration
      | attribute_specification
      | use_clause
      | group_type_declaration
      | group_declaration

您可能注意到信号声明未列出

该信号声明可以在架构声明部分中进行（在架构正文中紧跟保留字architecture之后的开始之前）

做出这种改变：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY work4 IS
PORT (  CS: IN STD_LOGIC;
        RD: IN STD_LOGIC;
        WR: IN STD_LOGIC;
        DATA : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
 END work4; 
ARCHITECTURE behav OF work4 IS 
    SIGNAL T: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN 

PROCESS(CS, RD,WR) 
--SIGNAL T: STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN 
 IF CS'EVENT AND CS = '1' THEN 
    IF WR='1' AND RD='0' THEN DATA<=T;
    ELSE IF WR='0' AND RD='1' THEN T<=DATA;
    END IF;
END IF;
END IF; 
 END PROCESS; 
 END behav;

IEEE库；
使用IEEE.STD_LOGIC_1164.ALL；
实体工作4是
端口（CS:STD_逻辑中；
RD：标准逻辑；
WR：标准逻辑中；
数据：输入标准逻辑向量（3到0）；
结束工作4；
work4的体系结构行为是
信号T:STD_逻辑_向量（3到0）；
开始
工艺（CS、RD、WR）
--信号T:STD_逻辑_向量（3到0）；
开始
如果CS'EVENT和CS='1'，则
如果WR='1'和RD='0'，则数据
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY work4 IS
PORT (  CS: IN STD_LOGIC;
        RD: IN STD_LOGIC;
        WR: IN STD_LOGIC;
        DATA : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
 END work4; 
ARCHITECTURE behav OF work4 IS 
    SIGNAL T: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN 

PROCESS(CS, RD,WR) 
--SIGNAL T: STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN 
 IF CS'EVENT AND CS = '1' THEN 
    IF WR='1' AND RD='0' THEN DATA<=T;
    ELSE IF WR='0' AND RD='1' THEN T<=DATA;
    END IF;
END IF;
END IF; 
 END PROCESS; 
 END behav;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY work4 IS
PORT (  CS: IN STD_LOGIC;
        RD: IN STD_LOGIC;
        WR: IN STD_LOGIC;
        DATA : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
 END work4; 
ARCHITECTURE behav OF work4 IS 
--    SIGNAL T: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN 

PROCESS(CS, RD,WR) 
--SIGNAL T: STD_LOGIC_VECTOR(3 DOWNTO 0);
    variable T: std_logic_vector (3 downto 0);
BEGIN 
 IF CS'EVENT AND CS = '1' THEN 
    IF WR='1' AND RD='0' THEN DATA <= T;
    ELSE IF WR='0' AND RD='1' THEN T := DATA;
    END IF;
END IF;
END IF; 
 END PROCESS; 
 END behav;