VHDL警告我的输出未连接到任何驱动程序
我目前正在研制一种通用的n位纹波进位加法器。但是当我去模拟我的程序时，它说我的输出连接到任何驱动程序，并且我得到每个测试用例的U 这是我的ripple进位加法器代码：VHDL警告我的输出未连接到任何驱动程序,vhdl,modelsim,Vhdl,Modelsim,我目前正在研制一种通用的n位纹波进位加法器。但是当我去模拟我的程序时，它说我的输出连接到任何驱动程序，并且我得到每个测试用例的U 这是我的ripple进位加法器代码： library ieee; use ieee.std_logic_1164.all; entity adder is generic ( WIDTH : positive := 8); port ( x, y : in std_logic_vector(WIDTH-1 down
library ieee;
use ieee.std_logic_1164.all;
entity adder is
generic (
WIDTH : positive := 8);
port (
x, y : in std_logic_vector(WIDTH-1 downto 0);
cin : in std_logic;
s : out std_logic_vector(WIDTH-1 downto 0);
cout : out std_logic);
end adder;
architecture RIPPLE_CARRY of adder is
signal temp_carry : std_logic_vector(width downto 0);
begin -- RIPPLE_CARRY
U_ADD : for i in 0 to width-1 generate
U_FA : entity work.fa port map (
input1 => x(i),
input2 => y(i),
carry_in => temp_carry(i),
sum => s(i),
carry_out => temp_carry(i+1)
);
end generate U_ADD;
temp_carry(0) <= cin;
cout <= temp_carry(width);
end RIPPLE_CARRY;
library ieee;
use ieee.std_logic_1164.all;
-- DO NOT CHANGE ANYTHING IN THE ENTITY
entity fa is
port (
input1 : in std_logic;
input2 : in std_logic;
carry_in : in std_logic;
sum : out std_logic;
carry_out : out std_logic);
end fa;
-- DEFINE THE FULL ADDER HERE
architecture BHV of fa is
begin
carry_out <= (input1 and input2) or (input1 and carry_in) or (input2
and carry_in);
sum <= (input1 xor input2) xor carry_in;
end BHV;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder_tb is
end adder_tb;
architecture TB of adder_tb is
component adder
generic (
WIDTH : positive := 8);
port (
x, y : in std_logic_vector(WIDTH-1 downto 0);
cin : in std_logic;
s : out std_logic_vector(WIDTH-1 downto 0);
cout : out std_logic);
end component;
constant TEST_WIDTH : positive := 8;
constant TEST_WIDTH2 : positive := 4;
signal x, y : std_logic_vector(TEST_WIDTH-1 downto 0);
signal x2, y2 : std_logic_vector(TEST_WIDTH2-1 downto 0);
signal cin : std_logic;
signal s_rc : std_logic_vector(TEST_WIDTH-1 downto 0);
signal s_rc2 : std_logic_vector(TEST_WIDTH2-1 downto 0);
signal s_cl : std_logic_vector(TEST_WIDTH-1 downto 0);
signal s_cl2 : std_logic_vector(TEST_WIDTH2-1 downto 0);
signal s_h : std_logic_vector(TEST_WIDTH-1 downto 0);
signal cout_rc, cout_rc2 : std_logic;
signal cout_cl, cout_cl2 : std_logic;
signal cout_h, cout_h2 : std_logic;
begin -- TB
U_RIPPLE_CARRY1 : adder
generic map (
WIDTH => TEST_WIDTH)
port map (
x => x,
y => y,
cin => cin,
s => s_rc,
cout => cout_rc);
U_RIPPLE_CARRY2 : adder
generic map (
WIDTH => TEST_WIDTH2)
port map (
x => x2,
y => y2,
cin => cin,
s => s_rc2,
cout => cout_rc2);
U_CARRY_LOOKAHEAD1 : adder
generic map (
WIDTH => TEST_WIDTH)
port map (
x => x,
y => y,
cin => cin,
s => s_cl,
cout => cout_cl);
U_CARRY_LOOKAHEAD2 : adder
generic map (
WIDTH => TEST_WIDTH2)
port map (
x => x2,
y => y2,
cin => cin,
s => s_cl2,
cout => cout_cl2);
U_HIERARCHICAL : adder
generic map (
WIDTH => 8) -- this architecture ignores the
-- generic, fixed to size 8
port map (
x => x,
y => y,
cin => cin,
s => s_h,
cout => cout_h);
process
variable error_rc : integer;
variable error_cl : integer;
variable error_h : integer;
variable result_tmp : unsigned(TEST_WIDTH downto 0);
variable result_tmp2 : unsigned(TEST_WIDTH2 downto 0);
variable correct_result : std_logic_vector(TEST_WIDTH-1 downto 0);
variable correct_result2 : std_logic_vector(TEST_WIDTH2-1 downto 0);
variable correct_cout : std_logic;
variable score_rc : integer;
variable score_cla : integer;
variable score_h : integer;
begin
error_rc := 0;
error_cl := 0;
error_h := 0;
report "******************TESTING WIDTH = 8********************";
for i in 0 to TEST_WIDTH-1 loop
x <= std_logic_vector(to_unsigned(i, TEST_WIDTH));
for j in 0 to TEST_WIDTH-1 loop
y <= std_logic_vector(to_unsigned(j, TEST_WIDTH));
for k in 0 to 1 loop
cin <= std_logic(to_unsigned(k, 1)(0));
wait for 10 ns;
result_tmp := unsigned("0"&x) + unsigned("0"&y) + to_unsigned(k, 1);
correct_result := std_logic_vector(result_tmp(TEST_WIDTH-1 downto 0));
correct_cout := std_logic(result_tmp(TEST_WIDTH));
if (s_rc /= correct_result) then
error_rc := error_rc + 1;
report "Error : RC, " & integer'image(i) & " + " & integer'image(j) & " + " & integer'image(k) & " = " & integer'image(to_integer(unsigned(s_rc))) severity warning;
end if;
if (cout_rc /= correct_cout) then
error_rc := error_rc + 1;
report "Error : RC, carry from " & integer'image(i) & " + " & integer'image(j) & " + " & integer'image(k) & " = " & std_logic'image(cout_rc) severity warning;
end if;
if (s_cl /= correct_result) then
error_cl := error_cl + 1;
report "Error : CL, " & integer'image(i) & " + " & integer'image(j) & " + " & integer'image(k) & " = " & integer'image(to_integer(unsigned(s_cl))) severity warning;
end if;
if (cout_cl /= correct_cout) then
error_cl := error_cl + 1;
report "Error : CL, carry from " & integer'image(i) & " + " & integer'image(j) & " + " & integer'image(k) & " = " & std_logic'image(cout_cl) severity warning;
end if;
if (s_h /= correct_result) then
error_h := error_h + 1;
report "Error : HEIR, " & integer'image(i) & " + " & integer'image(j) & " + " & integer'image(k) & " = " & integer'image(to_integer(unsigned(s_h))) severity warning;
end if;
if (cout_h /= correct_cout) then
error_h := error_h + 1;
report "Error : HEIR, carry from " & integer'image(i) & " + " & integer'image(j) & " + " & integer'image(k) & " = " & std_logic'image(cout_h) severity warning;
end if;
end loop; -- k
end loop; -- j
end loop; -- i
report "******************TESTING WIDTH = 4********************";
-- Test a different width
for i in 0 to TEST_WIDTH2-1 loop
x2 <= std_logic_vector(to_unsigned(i, TEST_WIDTH2));
for j in 0 to TEST_WIDTH2-1 loop
y2 <= std_logic_vector(to_unsigned(j, TEST_WIDTH2));
for k in 0 to 1 loop
cin <= std_logic(to_unsigned(k, 1)(0));
wait for 10 ns;
result_tmp2 := unsigned("0"&x2) + unsigned("0"&y2) + to_unsigned(k, 1);
correct_result2 := std_logic_vector(result_tmp2(TEST_WIDTH2-1 downto 0));
correct_cout := std_logic(result_tmp2(TEST_WIDTH2));
if (s_rc2 /= correct_result2) then
error_rc := error_rc + 1;
report "Error : RC, " & integer'image(i) & " + " & integer'image(j) & " + " & integer'image(k) & " = " & integer'image(to_integer(unsigned(s_rc2))) severity warning;
end if;
if (cout_rc2 /= correct_cout) then
error_rc := error_rc + 1;
report "Error : RC, carry from " & integer'image(i) & " + " & integer'image(j) & " + " & integer'image(k) & " = " & std_logic'image(cout_rc2) severity warning;
end if;
if (s_cl2 /= correct_result2) then
error_cl := error_cl + 1;
report "Error : CL, " & integer'image(i) & " + " & integer'image(j) & " + " & integer'image(k) & " = " & integer'image(to_integer(unsigned(s_cl2))) severity warning;
end if;
if (cout_cl2 /= correct_cout) then
error_cl := error_cl + 1;
report "Error : CL, carry from " & integer'image(i) & " + " & integer'image(j) & " + " & integer'image(k) & " = " & std_logic'image(cout_cl2) severity warning;
end if;
end loop; -- k
end loop; -- j
end loop; -- i
report "Ripple carry errors : " & integer'image(error_rc);
report "Carry lookahead errors : " & integer'image(error_cl);
report "Heirarchical errors : " & integer'image(error_h);
score_rc := 20 - error_rc;
score_cla := 30 - error_cl;
score_h := 50 - error_h;
if score_rc < 0 then
score_rc := 0;
end if;
if score_cla < 0 then
score_cla := 0;
end if;
if score_h < 0 then
score_h := 0;
end if;
report "RIPPLE_CARRY SCORE = " & integer'image(score_rc);
report "CLA SCORE = " & integer'image(score_cla);
report "HEIRARCHICAL SCORE = " & integer'image(score_h);
wait;
end process;
end TB;
configuration TB_CONFIG of adder_tb is
for TB
for U_RIPPLE_CARRY1 : adder
use entity work.adder(RIPPLE_CARRY);
end for;
for U_RIPPLE_CARRY2 : adder
use entity work.adder(RIPPLE_CARRY);
end for;
for U_CARRY_LOOKAHEAD1 : adder
use entity work.adder(CARRY_LOOKAHEAD);
end for;
for U_CARRY_LOOKAHEAD2 : adder
use entity work.adder(CARRY_LOOKAHEAD);
end for;
for U_HIERARCHICAL : adder
use entity work.adder(HIERARCHICAL);
end for;
end for;
end TB_CONFIG;
如果我使用测试台，并从测试台上移除所有未连接的元件，模拟工作将非常完美： **注：*************测试宽度=8******************** 时间：0 ps迭代：0实例：/adder\u tb **注：*************测试宽度=4******************** 时间：1280 ns迭代：0实例：/adder\u tb **注意：纹波进位错误：0 时间：1600 ns迭代：0实例：/adder\u tb **注：RIPPLE_进位分数=20 时间：1600 ns迭代：0实例：/adder\u tb
代码一眼看上去就可以了。在编译加法器之前，检查FA的正确版本是否编译到正确的位置；您看到的情况表明并非如此。请向我们展示加法器。\u tb。添加了测试台，我打算为该项目实施其他加法器的测试。FA工作我已经为之前的项目测试过，所以这不是问题所在。它也在我的modelsim项目的工作库中，并且已经编译。当尝试模拟加法器tb而不是tb_配置，或者在配置tb_配置的配置规范中注释架构绑定并模拟tb_配置时，您的测试台通过。
library ieee;
use ieee.std_logic_1164.all;
entity adder_tb is
end adder_tb;
architecture TB of adder_tb is
component adder
generic (
WIDTH : positive := 8);
port (
x, y : in std_logic_vector(WIDTH-1 downto 0);
cin : in std_logic;
s : out std_logic_vector(WIDTH-1 downto 0);
cout : out std_logic);
end component;
constant TEST_WIDTH : positive := 8;
constant TEST_WIDTH2 : positive := 4;
signal x, y : std_logic_vector(TEST_WIDTH-1 downto 0);
signal x2, y2 : std_logic_vector(TEST_WIDTH2-1 downto 0);
signal cin : std_logic;
signal s_rc : std_logic_vector(TEST_WIDTH-1 downto 0);
signal s_rc2 : std_logic_vector(TEST_WIDTH2-1 downto 0);
signal cout_rc, cout_rc2 : std_logic;
begin -- TB
U_RIPPLE_CARRY1 : adder
generic map (
WIDTH => TEST_WIDTH)
port map (
x => x,
y => y,
cin => cin,
s => s_rc,
cout => cout_rc);
U_RIPPLE_CARRY2 : adder
generic map (
WIDTH => TEST_WIDTH2)
port map (
x => x2,
y => y2,
cin => cin,
s => s_rc2,
cout => cout_rc2);
process
variable error_rc : integer;
use ieee.numeric_std.all;
variable result_tmp : unsigned(TEST_WIDTH downto 0);
variable result_tmp2 : unsigned(TEST_WIDTH2 downto 0);
variable correct_result : std_logic_vector(TEST_WIDTH-1 downto 0);
variable correct_result2 : std_logic_vector(TEST_WIDTH2-1 downto 0);
variable correct_cout : std_logic;
variable score_rc : integer;
begin
error_rc := 0;
report "******************TESTING WIDTH = 8********************";
for i in 0 to TEST_WIDTH-1 loop
x <= std_logic_vector(to_unsigned(i, TEST_WIDTH));
for j in 0 to TEST_WIDTH-1 loop
y <= std_logic_vector(to_unsigned(j, TEST_WIDTH));
for k in 0 to 1 loop
cin <= std_logic(to_unsigned(k, 1)(0));
wait for 10 ns;
result_tmp := unsigned("0"&x) + unsigned("0"&y) + to_unsigned(k, 1);
correct_result := std_logic_vector(result_tmp(TEST_WIDTH-1 downto 0));
correct_cout := std_logic(result_tmp(TEST_WIDTH));
if (s_rc /= correct_result) then
error_rc := error_rc + 1;
report "Error : RC, " & integer'image(i) & " + " & integer'image(j) & " + " & integer'image(k) & " = " & integer'image(to_integer(unsigned(s_rc))) severity warning;
end if;
if (cout_rc /= correct_cout) then
error_rc := error_rc + 1;
report "Error : RC, carry from " & integer'image(i) & " + " & integer'image(j) & " + " & integer'image(k) & " = " & std_logic'image(cout_rc) severity warning;
end if;
end loop; -- k
end loop; -- j
end loop; -- i
report "******************TESTING WIDTH = 4********************";
-- Test a different width
for i in 0 to TEST_WIDTH2-1 loop
x2 <= std_logic_vector(to_unsigned(i, TEST_WIDTH2));
for j in 0 to TEST_WIDTH2-1 loop
y2 <= std_logic_vector(to_unsigned(j, TEST_WIDTH2));
for k in 0 to 1 loop
cin <= std_logic(to_unsigned(k, 1)(0));
wait for 10 ns;
result_tmp2 := unsigned("0"&x2) + unsigned("0"&y2) + to_unsigned(k, 1);
correct_result2 := std_logic_vector(result_tmp2(TEST_WIDTH2-1 downto 0));
correct_cout := std_logic(result_tmp2(TEST_WIDTH2));
if (s_rc2 /= correct_result2) then
error_rc := error_rc + 1;
report "Error : RC, " & integer'image(i) & " + " & integer'image(j) & " + " & integer'image(k) & " = " & integer'image(to_integer(unsigned(s_rc2))) severity warning;
end if;
if (cout_rc2 /= correct_cout) then
error_rc := error_rc + 1;
report "Error : RC, carry from " & integer'image(i) & " + " & integer'image(j) & " + " & integer'image(k) & " = " & std_logic'image(cout_rc2) severity warning;
end if;
end loop; -- k
end loop; -- j
end loop; -- i
report "Ripple carry errors : " & integer'image(error_rc);
score_rc := 20 - error_rc;
if score_rc < 0 then
score_rc := 0;
end if;
report "RIPPLE_CARRY SCORE = " & integer'image(score_rc);
wait;
end process;
end TB;
configuration TB_CONFIG of adder_tb is
for TB
for U_RIPPLE_CARRY1 : adder
use entity work.adder(RIPPLE_CARRY);
end for;
for U_RIPPLE_CARRY2 : adder
use entity work.adder(RIPPLE_CARRY);
end for;
end for;
end TB_CONFIG;