Vhdl 错误：HDLCompiler:806-第35行：“函数”附近的语法错误。找不到语法错误
我一小时前刚刚合成并运行了这段代码。我使用双涉猎方法来显示我的FPGA板上7段显示器上正在计数的数字。我添加了seven.seg.display函数，并注释掉了它，现在它不会合成。我绞尽脑汁想弄明白这个语法错误可能是什么，但我再也做不到了。事实上我什么都没改，也没用。请帮帮我Vhdl 错误：HDLCompiler:806-第35行：“函数”附近的语法错误。找不到语法错误,vhdl,Vhdl,我一小时前刚刚合成并运行了这段代码。我使用双涉猎方法来显示我的FPGA板上7段显示器上正在计数的数字。我添加了seven.seg.display函数，并注释掉了它，现在它不会合成。我绞尽脑汁想弄明白这个语法错误可能是什么，但我再也做不到了。事实上我什么都没改，也没用。请帮帮我 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity main is Port ( reset : in STD_LOG
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity main is
Port ( reset : in STD_LOGIC;
clock : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR(7 downto 0)
);
end main;
function to.bcd(bin: std_logic_vector(7 downto 0));
variable i: integer:= 0;
variable bcd: std_logic_vector(11 downto 0):= (others => '0');
variable bint: std_logic_vector(7 downto 0):= bin;
begin
for i in 0 to 7 loop
bcd(11 downto 1):= bcd(10 downto 0);
bcd(0):= bint(7);
bint(7 downto 0):= bint(6 downto 0);
bint(0):= '0';
if(i < 7 and bcd(3 downto 0) > "0100") then
bcd(3 downto 0):= bcd(3 downto 0) + "0011";
end if;
if(i < 7 and bcd(7 downto 4) > "0100") then
bcd(7 downto 4):= bcd(7 downto 4) + "0011";
end if;
if(i < 7 and bcd(11 downto 8) > "0100") then
bcd(11 downto 8):= bcd(11 downto 8) + "0011";
end if;
end loop;
return bcd;
end to.bcd;
--function seven.seg.display(bin: std_logic_vector(6 downto 0));
-- variable bcd: std_logic_vector(11 downto 0):= (others => '0');
-- variable segment: std_logic_vector(6 downto 0):= bin;
--
--begin
-- case bcd(11 downto 8) is
-- when "0000"=> segment <="0000001"; -- 0
-- when "0001"=> segment <="1001111"; -- 1
-- when "0010"=> segment <="0010010"; -- 2
-- when "0011"=> segment <="0000110"; -- 3
-- when "0100"=> segment <="1001100"; -- 4
-- when "0101"=> segment <="0100100"; -- 5
-- when "0110"=> segment <="0100000"; -- 6
-- when "0111"=> segment <="0001111"; -- 7
-- when "1000"=> segment <="0000000"; -- 8
-- when "1001"=> segment <="0000100"; -- 9
-- when others=> segment <="1111111"; -- -
-- end case;
-- case bcd(7 downto 4) is
-- when "0000"=> segment <="0000001"; -- 0
-- when "0001"=> segment <="1001111"; -- 1
-- when "0010"=> segment <="0010010"; -- 2
-- when "0011"=> segment <="0000110"; -- 3
-- when "0100"=> segment <="1001100"; -- 4
-- when "0101"=> segment <="0100100"; -- 5
-- when "0110"=> segment <="0100000"; -- 6
-- when "0111"=> segment <="0001111"; -- 7
-- when "1000"=> segment <="0000000"; -- 8
-- when "1001"=> segment <="0000100"; -- 9
-- when others=> segment <="1111111"; -- -
-- end case;
-- case bcd(3 downto 0) is
-- when "0000"=> segment <="0000001"; -- 0
-- when "0001"=> segment <="1001111"; -- 1
-- when "0010"=> segment <="0010010"; -- 2
-- when "0011"=> segment <="0000110"; -- 3
-- when "0100"=> segment <="1001100"; -- 4
-- when "0101"=> segment <="0100100"; -- 5
-- when "0110"=> segment <="0100000"; -- 6
-- when "0111"=> segment <="0001111"; -- 7
-- when "1000"=> segment <="0000000"; -- 8
-- when "1001"=> segment <="0000100"; -- 9
-- when others=> segment <="1111111"; -- -
-- end case;
--
--return bcd;
--end seven.seg.display;
architecture Behavioral of main is
signal counter: std_logic_vector(7 downto 0);
signal prescaler: std_logic_vector(25 downto 0);
begin
CounterProcess: process(clock)
begin
if rising_edge(clock) then
if (reset = '1') then
prescaler <= (others => '0');
counter <= (others => '0');
else
if prescaler < "1011111010111100001000000" then
prescaler <= std_logic_vector(unsigned(prescaler) + 1);
else
prescaler <= (others => '0');
counter <= std_logic_vector(unsigned(counter) + 1);
end if;
end if;
end if;
end process;
LED <= counter;
end Behavioral;
函数to.bcd的语法错误，您必须编写：
function to.bcd(bin: std_logic_vector(7 downto 0)) return std_logic_vector(11 downto 0) is
[...]
begin
[...]
end to.bcd;
干杯您的功能不是主要单元。声明它最容易的地方是在架构声明区域 正如第一个答案指出的那样，函数没有返回类型声明，或者关键字是，标识符中不能有句点，句点是分隔符 因为您没有包含另一个use子句，所以我将三个+的加法从数字\u std转换为unsigned。当您的第二个答案尝试清楚地表达时，您可以使用use子句来启用对包std\u logic\u unsigned的访问，但这将要求您在counterprocess中更改+，除非您添加一个use子句作为子程序函数声明项 而且有一个错误：
bint(7 downto 0) := bint(6 downto 0);
bint(7 downto 1) := bint(6 downto 0);
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity main is
port (
reset: in std_logic;
clock: in std_logic;
led: out std_logic_vector(7 downto 0)
);
end entity;
architecture behavioral of main is
signal counter: std_logic_vector(7 downto 0);
signal prescaler: std_logic_vector(25 downto 0 );
function to_bcd (bin: std_logic_vector(7 downto 0)) return std_logic_vector is
variable i: integer:= 0;
variable bcd: std_logic_vector(11 downto 0):= (others => '0');
variable bint: std_logic_vector(7 downto 0):= bin;
begin
for i in 0 to 7 loop
bcd(11 downto 1) := bcd(10 downto 0);
bcd(0) := bint(7);
bint(7 downto 1) := bint(6 downto 0);
bint(0) := '0';
if i < 7 and bcd(3 downto 0) > "0100" then
bcd(3 downto 0) :=
std_logic_vector (unsigned(bcd(3 downto 0)) + "0011");
end if;
if i < 7 and bcd(7 downto 4) > "0100" then
bcd(7 downto 4) :=
std_logic_vector(unsigned(bcd(7 downto 4)) + "0011");
end if;
if i < 7 and bcd(11 downto 8) > "0100" then
bcd(11 downto 8) :=
std_logic_vector(unsigned(bcd(11 downto 8)) + "0011");
end if;
end loop;
return bcd;
end function;
begin
counterprocess:
process(clock)
begin
if rising_edge(clock) then
if (reset = '1') then
prescaler <= (others => '0');
counter <= (others => '0');
else
if prescaler < "1011111010111100001000000" then
prescaler <= std_logic_vector(unsigned(prescaler) + 1);
else
prescaler <= (others => '0');
counter <= std_logic_vector(unsigned(counter) + 1);
end if;
end if;
end if;
end process;
led <= counter;
end architecture;
您的VHDL规范现在可以进行分析和阐述。它还没有经过功能测试。to_bcd函数看起来像是VHDL专家博客上的函数。我尝试了你的建议，但它仍然让编译器不高兴：谢谢，谢谢！它现在工作正常。我很高兴你有时间帮助我。