我的VHDL代码的输出取决于重置

又是我！ 首先，我想说，我几天前学过VHDL，在这方面我是个新手，所以我倾向于犯愚蠢的错误。任何建议都很好。 我已经为一个可以用作内存控制器的模块编写了VHDL代码

这是我的密码：

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memory_controller is
port(clk: in std_logic;
     reset: in std_logic;
     bus_id: in std_logic_vector(7 downto 0);
     read_write, burst: in std_logic;
     ready: in std_logic;
     oe, we: out std_logic;
     addr_1, addr_2: out std_logic_vector(7 downto 0)
     );
end memory_controller;
architecture behavioral of memory_controller is
    type statetype is (idle, decision, wr, rd1, rd2, rd3, rd4);
    signal present_state, next_state : statetype;
    signal addr_int : integer range 0 to (2**addr_1'length)-1;
    begin
    Synch_reset: process(clk)
    begin
        if (rising_edge(clk)) then
            if (reset ='0') then
                present_state <= next_state;  
            else
                present_state <= idle;   
            end if;
        end if;
    end process;  
    decision_logic: process(present_state, read_write, ready, burst)
    begin
        case present_state is
            when idle => 
                oe <= '0'; we <= '0'; addr_int <= 0;
                addr_1 <= std_logic_vector(to_unsigned(addr_int, addr_1'length));
                addr_2 <= std_logic_vector(to_unsigned(addr_int, addr_2'length));
                if(bus_id = "11110011") then
                    next_state <= decision;
                else
                    next_state <= idle;
                end if;
            when decision =>
                if (read_write = '1') then 
                    next_state <= rd1;
                else 
                    next_state <= wr;
                end if;
            when wr =>
                we <= '1';
                if (ready = '1') then 
                    next_state <= idle;
                else
                    next_state <= wr;
                end if;
            when rd1 =>
                oe <= '1';
                if(ready = '0') then
                    next_state <= rd1;
                else
                    if(burst = '0') then
                        next_state <= idle;
                    else 
                        next_state <= rd2;
                        addr_int <= addr_int + 1;
                addr_1 <= std_logic_vector(to_unsigned(addr_int, addr_1'length));
                addr_2 <= std_logic_vector(to_unsigned(addr_int, addr_2'length));
                    end if;
                end if;
            when rd2 =>
                oe <= '1';
                if(ready = '1') then
                    next_state <= rd3;
                    addr_int <= addr_int + 1;
                addr_1 <= std_logic_vector(to_unsigned(addr_int, addr_1'length));
                addr_2 <= std_logic_vector(to_unsigned(addr_int, addr_2'length));
                else
                    next_state <= rd2;
                end if;
            when rd3 =>
                oe <= '1';
                if(ready = '1') then 
                    next_state <= rd4;
                    addr_int <= addr_int + 1;
                addr_1 <= std_logic_vector(to_unsigned(addr_int, addr_1'length));
                addr_2 <= std_logic_vector(to_unsigned(addr_int, addr_2'length));
                else
                    next_state <= rd3;
                end if;
            when rd4 =>
                oe <= '1';
                if(ready = '1') then 
                    next_state <= idle;
                else 
                    next_state <= rd4;
                end if;
         end case;
     end process;
end behavioral;

IEEE库；
使用IEEE.std_logic_1164.all；
使用IEEE.std_logic_arith.all；
使用IEEE.std_logic_unsigned.all；
使用ieee.numeric_std.all；
实体内存控制器是
端口（时钟：在标准逻辑中；
复位：在标准逻辑中；
总线id：在标准逻辑向量中（7到0）；
读写、突发：在标准逻辑中；
就绪：在标准逻辑中；
oe，we：输出标准逻辑；
地址1，地址2：输出标准逻辑向量（7到0）
);
终端存储器控制器；
内存控制器的体系结构是
类型statetype为（空闲、决策、wr、rd1、rd2、rd3、rd4）；
信号当前状态、下一状态：statetype；
信号地址：整数范围0到（2**addr_1'长度）-1；
开始
同步复位：进程（时钟）
开始
如果（上升沿（clk）），则
如果（reset='0'），则
当前状态您有一个组合循环：您在组合过程中读取和写入信号
addr\u int
，这会导致各种问题。创建一个信号
next\u addr\u int
并在时钟进程中分配该信号，或者将所有内容都放在一个时钟进程中

代码的其他问题：


std\u logic\u arith
和
std\u logic\u unsigned
不推荐使用。改用ieee.numeric\u std

---

像这样的转换使代码很难理解：

addr\u 1。去掉“等待5ns”，改为“等待上升沿（clk）”。这样，您将确保不会出现任何增量周期问题。2.您的控制器代码有点狡猾：我确信您希望addr_int（至少）成为一个寄存器，否则您的计数器会做一些有趣的事情。然后回来；-）我认为你在写软件，而不是硬件。请仔细阅读你的书：有些信号是赋值的，比如
a
Library IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memory_controller_tb is
end memory_controller_tb;
architecture test of memory_controller_tb is
component memory_controller
port(clk: in std_logic;
     reset: in std_logic;
     bus_id: in std_logic_vector(7 downto 0);
     read_write, burst: in std_logic;
     ready: in std_logic;
     oe, we: out std_logic;
     addr_1, addr_2: out std_logic_vector(7 downto 0)
     );
end component;
signal clk: std_logic;
signal reset: std_logic;
signal read_write, burst, oe, we: std_logic;
signal addr_1, addr_2: std_logic_vector(7 downto 0);
signal ready: std_logic;
signal bus_id: std_logic_vector(7 downto 0);
signal StopClock : boolean := FALSE;
begin
UUT :memory_controller
port map( clk => clk,
          reset => reset,
          bus_id => bus_id,
          read_write => read_write,
          burst => burst,
          ready => ready,
          oe => oe,
          we => we,
          addr_1 => addr_1,
          addr_2 => addr_2);
clk_process: process
begin
while not StopClock loop
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end loop;
end process clk_process;
stim: process is
begin
reset <= '1', '0' after 50 ns;
bus_id <= "11110011";
wait for 5 ns;
read_write <= '0';
wait for 5 ns;
ready <= '1';
bus_id <= "11110011";
wait for 5 ns;
read_write <= '1';
assert (ready <='1' and burst <= '1')
report "Illegal state"
severity error;
assert (ready <= '1' and burst <='0')
report "Illegal state"
severity error;
wait for 5 ns;
ready <= '0';
wait for 5 ns;
burst <= '0';
wait for 5 ns;
ready <= '1';
wait for 5 ns;
burst <= '1';
wait for 5 ns;
ready <= '0';
wait for 5 ns;
ready <= '1';
wait for 5 ns;
ready <= '1';
end process;
end test;

configuration CFG_memory_controller of memory_controller_tb is
    for test
        for UUT : memory_controller
        end for;
    end for;
end;