Arrays 使用generate语句创建';n';VHDL中的寄存器数组
我正在将一个旧的AHDL代码转换为VHDL,我需要使用Arrays 使用generate语句创建';n';VHDL中的寄存器数组,arrays,vhdl,intel-fpga,flip-flop,Arrays,Vhdl,Intel Fpga,Flip Flop,我正在将一个旧的AHDL代码转换为VHDL,我需要使用generate语句创建5个电阻阵列。我以前从未使用过generate,尝试了几个小时后,我仍然找不到问题的答案。我最初的方法是使用一个18位的输入数组和一个18位的输出数组,但我知道这不是实现的方法 这是我现在掌握的代码: entity setup_comp_reg is generic( NUM_ID: integer := 18 ); port ( clk: in std_logic;
generate
语句创建5个电阻阵列。我以前从未使用过generate
,尝试了几个小时后,我仍然找不到问题的答案。我最初的方法是使用一个18位的输入数组和一个18位的输出数组,但我知道这不是实现的方法
这是我现在掌握的代码:
entity setup_comp_reg is
generic(
NUM_ID: integer := 18
);
port (
clk: in std_logic;
D: in std_logic_vector(17 downto 0);
clrn: in std_logic;
ena: in std_logic;
Q: out std_logic_vector(17 downto 0)
);
end setup_comp_reg;
architecture rtl of setup_comp_reg is
begin
DFFE: process (clk, clrn, ena) -- 18 times, using generate
begin
if (clrn = '0') then
Q<= (others => '0');
elsif (rising_edge(clk)) then
if (ena = '1') then
Q<= D;
end if;
end if;
end process;
end rtl;
谢谢。AHDL generate语句为i的每个迭代表示四个触发器 AHDL生成语句:
for i in 17 to 0 generate
rg_bit_time[i].(d, clk, clrn, ena) = (iDATA[i], clk, not reg_reset, adBT&iWR);
rg_sample_time[i].(d, clk, clrn, ena) = (iDATA[i], clk, not reg_reset, adSP&iWR);
rg_low_sync[i].(d, clk, clrn, ena) = (iDATA[i], clk, not reg_reset, adLS&iWR);
rg_hi_sync[i].(d, clk, clrn, ena) = (iDATA[i], clk, not reg_reset, adHS&iWR);
end generate;
AHDL使用函数原型来表示原语(这里是DFFE)。返回值将是q输出(AHDL generate语句中没有提到)。对于具有函数原型关联的名称,有四个赋值。这表示由18个触发器组成的四个阵列
DFFE寄存器的功能原型如第3节基本体、触发器和锁存基本体表3-9所示。MAX+PLUS II触发器和闩锁:
其中,返回值将与AHDL generate语句中赋值语句中的名称(例如rg_bit_time[i])相关联
在VHDL中,我们可以通过将实际值与包含输出的DFFE实体的形式值相关联来实现这一点
带有所有输出和输入端口的行为表示形式如下所示:
library ieee; -- ADDED context clause
use ieee.std_logic_1164.all;
entity setup_comp_reg is
generic (
NUM_ID: integer := 18
);
port (
clk: in std_logic;
D: in std_logic_vector(NUM_ID - 1 downto 0);
clrn: in std_logic;
ena: in std_logic;
-- Q: out std_logic_vector(17 downto 0)
WR: in std_logic; -- ADDED
adBT: in std_logic; -- ADDED
adSP: in std_logic; -- ADDED
adLS: in std_logic; -- ADDED
adHS: in std_logic; -- ADDED
rg_bit_time: out std_logic_vector(NUM_ID - 1 downto 0); -- ADDED
rg_sample_time: out std_logic_vector(NUM_ID - 1 downto 0); -- ADDED
rg_low_sync: out std_logic_vector(NUM_ID - 1 downto 0); -- ADDED
rg_hi_sync: out std_logic_vector(NUM_ID - 1 downto 0) -- ADDED
);
end entity setup_comp_reg;
architecture rtl of setup_comp_reg is
-- For no -2008 dependency, ADD these:
signal adBTWR: std_logic;
signal adSPWR: std_logic;
signal adLSWR: std_logic;
signal adHSWR: std_logic;
begin
-- Write ENABLE conditions:
adBTWR <= adBT and WR;
adSPWR <= adSP and WR;
adLSWR <= adLS and WR;
adHSWR <= adHS and WR;
SETUP_REGS:
for i in NUM_ID - 1 downto 0 generate
BIT_TIME:
process (clk, clrn) -- enables not needed in sensitivity list
begin
if clrn = '0' then
rg_bit_time(i) <= '0';
elsif rising_edge (clk) then
if adBTWR = '1' then
rg_bit_time(i) <= D(i);
end if;
end if;
end process;
SAMPLE_TIME:
process (clk, clrn)
begin
if clrn = '0' then
rg_sample_time(i) <= '0';
elsif rising_edge (clk) then
if adSPWR = '1' then
rg_sample_time(i) <= D(i);
end if;
end if;
end process;
LOW_SYNC:
process (clk, clrn)
begin
if clrn = '0' then
rg_low_sync(i) <= '0';
elsif rising_edge (clk) then
if adLSWR = '1' then
rg_low_sync(i) <= D(i);
end if;
end if;
end process;
HI_SYNC:
process (clk, clrn)
begin
if clrn = '0' then
rg_hi_sync(i) <= '0';
elsif rising_edge (clk) then
if adHSWR = '1' then
rg_hi_sync(i) <= D(i);
end if;
end if;
end process;
end generate;
end architecture rtl;
库ieee;——添加上下文子句
使用ieee.std_logic_1164.all;
实体设置_comp_reg是
一般的(
NUM_ID:整数:=18
);
港口(
clk:标准逻辑中;
D:在标准逻辑向量中(NUM_ID-1到0);
clrn:标准逻辑中;
ena:标准逻辑;
--Q:输出标准逻辑向量(17到0)
WR:在标准逻辑中;--添加
adBT:在标准逻辑中;--添加
adSP:在标准逻辑中;--添加
adLS:在标准逻辑中;--添加
adHS:在标准逻辑中;--添加
rg_位时间:输出标准逻辑向量(NUM_ID-1向下至0);--添加
rg_样本_时间:输出标准逻辑_向量(NUM_ID-1向下至0);--添加
rg_low_sync:out std_logic_vector(NUM_ID-1向下到0);--添加
rg_hi_sync:out标准逻辑向量(NUM_ID-1到0)--添加
);
结束实体设置\u comp\u reg;
设置组件注册的体系结构rtl为
--对于no-2008依赖项,添加以下内容:
信号adBTWR:std_逻辑;
信号adSPWR:std_逻辑;
信号adLSWR:std_逻辑;
信号adHSWR:std_逻辑;
开始
--写入启用条件:
adBTWR您已经生成了18个DFFE,没有生成,因为D和Q是18位宽。你到底在问什么?如果你想要18个寄存器,每个寄存器有18位,你首先必须决定如何互连它们。我需要创建没有18位输入和输出的DFFE。旧的AHDL代码非常直截了当,我需要这样做(如下),因为我将有5个18位重寄存器数组。以下是AHDL:对于17到0中的i,生成rg_位时间[i]。(d,clk,clrn,ena)=(iDATA[i],clk,not reg_reset,enable[i]);终端生成;所以你需要18个一位寄存器。您仍然需要定义它们是如何相互关联的。如果您只需要18个单独的输入和18个单独的输出,您上面的代码就可以了,只需从这个模块上面的std\u logic\u vector
中选取位即可<代码>标准逻辑向量
只是对单个位的抽象;这是在更高级的语言中得到的。哪5个数组?哦,你编辑了评论。这就像果冻。我看不懂你的心思,请用你想做的事情和AHDL的等效内容更新问题。如果您需要5个setup_comp_reg实例,那么无论是单独实例化5次还是在一个for..generate语句中实例化5次都无关紧要。您的困惑似乎源于DFFE的AHDL优先级,它是用函数原型描述的:函数DFFE(d、clk、clrn、prn、ena)返回(q);。唯一挂起q输出名称的地方是赋值(它将VHDL中的形式与实际相关联)。看。名称将与q输出相关联。好的,这回答了我的问题。还有一件事,使用generate语句不如使用rtl2架构好吗?我应该去rtl2,对吗?感谢您的帮助。Actel的generate语句支持自底向上的设计(使用寄存器原语),这在VHDL中是不需要的,VHDL通过RTL合成支持隐含寄存器。缺乏RTL合成是AHDL的一个限制。这三种体系结构都将生成等效的网络列表。最后,当将更多的系统设计移植到相同的高密度现代设备或执行系统模拟时,rtl2更适合于模拟。
library ieee; -- ADDED context clause
use ieee.std_logic_1164.all;
entity setup_comp_reg is
generic (
NUM_ID: integer := 18
);
port (
clk: in std_logic;
D: in std_logic_vector(NUM_ID - 1 downto 0);
clrn: in std_logic;
ena: in std_logic;
-- Q: out std_logic_vector(17 downto 0)
WR: in std_logic; -- ADDED
adBT: in std_logic; -- ADDED
adSP: in std_logic; -- ADDED
adLS: in std_logic; -- ADDED
adHS: in std_logic; -- ADDED
rg_bit_time: out std_logic_vector(NUM_ID - 1 downto 0); -- ADDED
rg_sample_time: out std_logic_vector(NUM_ID - 1 downto 0); -- ADDED
rg_low_sync: out std_logic_vector(NUM_ID - 1 downto 0); -- ADDED
rg_hi_sync: out std_logic_vector(NUM_ID - 1 downto 0) -- ADDED
);
end entity setup_comp_reg;
architecture rtl of setup_comp_reg is
-- For no -2008 dependency, ADD these:
signal adBTWR: std_logic;
signal adSPWR: std_logic;
signal adLSWR: std_logic;
signal adHSWR: std_logic;
begin
-- Write ENABLE conditions:
adBTWR <= adBT and WR;
adSPWR <= adSP and WR;
adLSWR <= adLS and WR;
adHSWR <= adHS and WR;
SETUP_REGS:
for i in NUM_ID - 1 downto 0 generate
BIT_TIME:
process (clk, clrn) -- enables not needed in sensitivity list
begin
if clrn = '0' then
rg_bit_time(i) <= '0';
elsif rising_edge (clk) then
if adBTWR = '1' then
rg_bit_time(i) <= D(i);
end if;
end if;
end process;
SAMPLE_TIME:
process (clk, clrn)
begin
if clrn = '0' then
rg_sample_time(i) <= '0';
elsif rising_edge (clk) then
if adSPWR = '1' then
rg_sample_time(i) <= D(i);
end if;
end if;
end process;
LOW_SYNC:
process (clk, clrn)
begin
if clrn = '0' then
rg_low_sync(i) <= '0';
elsif rising_edge (clk) then
if adLSWR = '1' then
rg_low_sync(i) <= D(i);
end if;
end if;
end process;
HI_SYNC:
process (clk, clrn)
begin
if clrn = '0' then
rg_hi_sync(i) <= '0';
elsif rising_edge (clk) then
if adHSWR = '1' then
rg_hi_sync(i) <= D(i);
end if;
end if;
end process;
end generate;
end architecture rtl;
architecture rtl1 of setup_comp_reg is
-- For no -2008 dependency, ADD these:
signal adBTWR: std_logic;
signal adSPWR: std_logic;
signal adLSWR: std_logic;
signal adHSWR: std_logic;
begin
-- Write ENABLE conditions:
adBTWR <= adBT and WR;
adSPWR <= adSP and WR;
adLSWR <= adLS and WR;
adHSWR <= adHS and WR;
-- SETUP_REGS:
BIT_TIME:
process (clk, clrn) -- enables not needed in sensitivity list
begin
if clrn = '0' then
rg_bit_time <= (others => '0');
elsif rising_edge (clk) then
if adBTWR = '1' then
rg_bit_time <= D;
end if;
end if;
end process;
SAMPLE_TIME:
process (clk, clrn)
begin
if clrn = '0' then
rg_sample_time <= (others => '0');
elsif rising_edge (clk) then
if adSPWR = '1' then
rg_sample_time <= D;
end if;
end if;
end process;
LOW_SYNC:
process (clk, clrn)
begin
if clrn = '0' then
rg_low_sync <= (others => '0');
elsif rising_edge (clk) then
if adLSWR = '1' then
rg_low_sync <= D;
end if;
end if;
end process;
HI_SYNC:
process (clk, clrn)
begin
if clrn = '0' then
rg_hi_sync <= (others => '0');
elsif rising_edge (clk) then
if adHSWR = '1' then
rg_hi_sync <= D;
end if;
end if;
end process;
end architecture rtl1;
architecture rtl2 of setup_comp_reg is
signal adBTWR: std_logic;
signal adSPWR: std_logic;
signal adLSWR: std_logic;
signal adHSWR: std_logic;
begin
-- Write ENABLE conditions:
adBTWR <= adBT and WR;
adSPWR <= adSP and WR;
adLSWR <= adLS and WR;
adHSWR <= adHS and WR;
BT_SP_LS_HS:
process (clk, clrn) -- enables not needed in sensitivity list
begin
if clrn = '0' then
rg_bit_time <= (others => '0');
rg_sample_time <= (others => '0');
rg_low_sync <= (others => '0');
rg_hi_sync <= (others => '0');
elsif rising_edge (clk) then
if adBTWR = '1' then
rg_bit_time <= D;
end if;
if adSPWR = '1' then
rg_sample_time <= D;
end if;
if adLSWR = '1' then
rg_low_sync <= D;
end if;
if adHSWR = '1' then
rg_hi_sync <= D;
end if;
end if;
end process;
end architecture rtl2;