C Makefile找不到对象的规则
我有一个关于Makefile的初学者问题。我有一个非常简单的makefile,其中包含:C Makefile找不到对象的规则,c,makefile,rule,C,Makefile,Rule,我有一个关于Makefile的初学者问题。我有一个非常简单的makefile,其中包含: SHELL = /bin/sh CC = gcc CFLAGS = -lm -std=c99 -g -o0 EXEC = test BUILDDIR = build OBJDIR = obj SOURCES = $(shell cat sources.list) DEPS = $(shell cat headers.list) OBJ = $(SOURCES:.c=.o) OBJECTS = $(patsu
SHELL = /bin/sh
CC = gcc
CFLAGS = -lm -std=c99 -g -o0
EXEC = test
BUILDDIR = build
OBJDIR = obj
SOURCES = $(shell cat sources.list)
DEPS = $(shell cat headers.list)
OBJ = $(SOURCES:.c=.o)
OBJECTS = $(patsubst %,$(OBJDIR)/%,$(OBJ))
all: $(OBJECTS)
$(CC) $(CFLAGS) $(OBJECTS) -o $(BUILDDIR)/$(EXEC)
$(OBJDIR)/%.o: %.c $(DEPS)
$(CC) -c $< -o $@
clean:
rm -f $(BUILDDIR)/$(EXEC) $(OBJDIR)/*.o
我做错了什么
经过最初的几句评论和进一步的研究,我得到了这个工作版本,但是它没有在obj文件夹中创建对象文件,所以这不是我的目标
SHELL = /bin/sh
CC = gcc
CFLAGS = -lm -std=c99 -g -o0
EXEC = test
BUILDDIR = build
OBJDIR = obj
SOURCES = $(shell cat sources.list)
DEPS = $(shell cat headers.list)
OBJ = $(SOURCES:.c=.o)
OBJECTS = $(patsubst %,$(OBJDIR)/%,$(OBJ))
all: $(BUILDDIR)/$(EXEC)
$(BUILDDIR)/$(EXEC): $(OBJ)
$(CC) $(CFLAGS) $(OBJ) -o $(BUILDDIR)/$(EXEC)
%.o: %.c $(DEPS)
$(CC) -c $< -o $@
clean:
rm -f $(BUILDDIR)/$(EXEC) $(OBJDIR)/*.o
SHELL=/bin/sh
CC=gcc
CFLAGS=-lm-std=c99-g-o0
EXEC=测试
BUILDDIR=build
OBJDIR=obj
SOURCES=$(shell cat SOURCES.list)
DEPS=$(shell cat headers.list)
OBJ=$(来源:.c=.o)
对象=$(patsubst%,$(OBJDIR)/%,$(OBJ))
全部:$(BUILDDIR)/$(EXEC)
$(BUILDDIR)/$(EXEC):$(OBJ)
$(CC)$(CFLAGS)$(OBJ)-o$(BUILDDIR)/$(EXEC)
%.o:%.c$(DEPS)
$(CC)-c$<-o$@
清洁:
rm-f$(BUILDDIR)/$(EXEC)$(OBJDIR)/*.o
headers.list中的所有文件是否都位于正确的位置
顺便说一句,这不是处理标题依赖关系的好方法。您应该查看
-MP
和-MDD
以及预处理器的其他选项,以生成依赖项。一个经典的makefile,它可以满足您的需要:
SHELL=/bin/bash
CC=gcc
CFLAGS=-std=c99 -g -o0
LDFLAGS=-lm
EXEC=test
BUILDDIR=build/
OBJDIR=obj/
SOURCES=$(shell cat sources.list)
OBJECTS=$(patsubst %.c,$(OBJDIR)%.o,$(notdir $(SOURCES)))
vpath %.c $(sort $(dir $(SOURCES)))
.PHONY:all mrproper clean depends
all:$(BUILDDIR)$(EXEC)
$(BUILDDIR)$(EXEC):$(OBJECTS)|$(BUILDDIR)
$(CC) $(CFLAGS) $^ -o $@ $(LDFLAGS)
$(OBJDIR)%.o:%.c|$(OBJDIR)
$(CC) -c $< -o $@
$(BUILDDIR) $(OBJDIR):
mkdir $@
mrproper:clean
rm -f $(BUILDDIR)$(EXEC)
clean:
rm -f $(OBJECTS)
depends:
@rm -f dependencies.mk
@for i in $(SOURCES); do $(CC) -MM $$i -MT $(OBJDIR)`basename $$i | sed s:.c$$:.o:` >> dependencies.mk; done
include $(wildcard dependencies.mk)
Name.c
是否存在于顶级目录中?是的,否则makefile将不需要生成.o。您的源代码.list
文件中是否存在名称.c?根本无法解决问题,但是,-lm
应该位于variableLD\u FLAGS
中,而不是CFLAGS
。将全部替换为$(BUILDDIR)/$(EXEC)
在当前的all
规则中添加all
规则b在没有命令的情况下:all:$(BUILDDIR)/$(EXEC)
,并添加。PHONY
指令:。PHONY
设置非实际文件的目标列表。
SHELL=/bin/bash
CC=gcc
CFLAGS=-std=c99 -g -o0
LDFLAGS=-lm
EXEC=test
BUILDDIR=build/
OBJDIR=obj/
SOURCES=$(shell cat sources.list)
OBJECTS=$(patsubst %.c,$(OBJDIR)%.o,$(notdir $(SOURCES)))
vpath %.c $(sort $(dir $(SOURCES)))
.PHONY:all mrproper clean depends
all:$(BUILDDIR)$(EXEC)
$(BUILDDIR)$(EXEC):$(OBJECTS)|$(BUILDDIR)
$(CC) $(CFLAGS) $^ -o $@ $(LDFLAGS)
$(OBJDIR)%.o:%.c|$(OBJDIR)
$(CC) -c $< -o $@
$(BUILDDIR) $(OBJDIR):
mkdir $@
mrproper:clean
rm -f $(BUILDDIR)$(EXEC)
clean:
rm -f $(OBJECTS)
depends:
@rm -f dependencies.mk
@for i in $(SOURCES); do $(CC) -MM $$i -MT $(OBJDIR)`basename $$i | sed s:.c$$:.o:` >> dependencies.mk; done
include $(wildcard dependencies.mk)
make depends
make