Compiler construction Verilog测试台模拟误差

端模

我得到以下错误：

module stimulus;
reg [511:0]FROM_LS;
reg CLOCK;
reg [2:0]HMIC_CTRL;
reg [20:0]BRANCH_CTRL;
reg  [63:0]TO_IF_ID;
reg FLUSH_CTRL;
reg [20:0]TO_LS;

inst_line_buf ILB(FLUSH_CTRL,TO_LS,FROM_LS,CLOCK,HMIC_CTRL,BRANCH_CTRL,TO_IF_ID);

// setup clock
initial
 begin

  #10 CLOCK = ~CLOCK;

// apply stimulus

  FROM_LS[511:480]= 32'b00011_00000_00100_01100_11100_10111_01;
  FROM_LS[479:448]=32'b000_11000_00100_01111_11111_00011_1000;

  HMIC_CTRL[2:0]=3'b000;
  BRANCH_CTRL[20:0]=20'b00000_00000_00000_00000;
  #2 $display("FLUSH CONTROL=%b, TO_LS= %b",FLUSH_CTRL,TO_LS);
end

---

除非您向我们显示完整的错误消息，以及

vsim

命令行和一些相关的Verilog代码，否则我们所能提供的只是建议您在谷歌上搜索错误消息

例如，来自：

ModelSim模拟选项尚未启用 已正确设置（项目设置> ModelSim>选项）进行以下操作 更改：在模拟上单击鼠标右键 “项目流”窗口中的选项卡或 选择项目>设置>模拟 测试台模块名称：指定您的 测试台模块名称顶级 测试台中的实例名称： DUT的实例名称请参见 下面的屏幕截图是一个示例

更新：现在您添加了一些代码，

ILB

看起来可疑。首先将其用作

inst_line_buf

模块的实例名，然后在

initial

块中再次将其用作函数或任务调用。我猜您希望它位于

初始

块之外，但是使用端口连接：

# Loading work.inst_line_buf
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (512 or 512) does not match connection size (1) for port 'from_LS'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(1).
#         Region: /stimulus/ILB
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (21) for port 'clk'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(2).
#         Region: /stimulus/ILB
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (3 or 3) does not match connection size (512) for port 'hmic_ctrl'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(3).
#         Region: /stimulus/ILB
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (21 or 21) does not match connection size (1) for port 'branch_ctrl'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(4).
#         Region: /stimulus/ILB
# ** Error: (vsim-3053) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): Illegal output or inout port connection for "port 'to_if_id'".
#         Region: /stimulus/ILB
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (64 or 64) does not match connection size (3) for port 'to_if_id'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(5).
#         Region: /stimulus/ILB
# ** Error: (vsim-3053) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): Illegal output or inout port connection for "port 'flush_ctrl'".
#         Region: /stimulus/ILB
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (21) for port 'flush_ctrl'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(6).
#         Region: /stimulus/ILB
# ** Error: (vsim-3053) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): Illegal output or inout port connection for "port 'to_LS'".
#         Region: /stimulus/ILB
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (21 or 21) does not match connection size (64) for port 'to_LS'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(7).
#         Region: /stimulus/ILB
# Error loading design

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至少给我们看看警告信息@marty：我已经包括了testbench的代码，以及uasked中的错误。你能帮我解决这个问题吗？

inst_line_buf ILB (FROM_LS,CLOCK,HMIC_CTRL,TO_IF_ID,FLUSH_CTRL,TO_LS);