Functional programming 为有条件的信号添加功能覆盖_Functional Programming_Verilog_Code Coverage_Add_System Verilog

Functional programming 为有条件的信号添加功能覆盖

functional-programming verilog system-verilog

Functional programming 为有条件的信号添加功能覆盖,functional-programming,verilog,code-coverage,add,system-verilog,Functional Programming,Verilog,Code Coverage,Add,System Verilog,我不熟悉verilog系统的功能性覆盖。当两个信号不相等时，我想写一个覆盖组例如，每个信号有两个单独的覆盖范围 covergroup group1 @(posedge `TB_TOP.clk); cpb_1 : coverpoint `TB_TOP.sig1 { bins r_zero = {0}; bins r_one = {1}; endgroup covergroup group2 @(posedge `TB_TOP.c

我不熟悉verilog系统的功能性覆盖。当两个信号不相等时，我想写一个覆盖组

例如，每个信号有两个单独的覆盖范围

    covergroup group1 @(posedge `TB_TOP.clk); 
    cpb_1 : coverpoint `TB_TOP.sig1 {
        bins r_zero = {0};
        bins r_one = {1};
     endgroup
    covergroup group2 @(posedge `TB_TOP.clk); 
    cpb_2 : coverpoint `TB_TOP.sig2 {
        bins r_zero = {0};
        bins r_one = {1};
     endgroup

现在我想添加另一个，当sig1不等于时钟边缘的sig2时。

谢谢你是说这样的事吗

covergroup group3 @(posedge `TB_TOP.clk);
  // coverpoint can take an expression, so provide sig1!=sig2
  cpb_3: coverpoint (`TB_TOP.sig1 != `TB_TOP.sig2) {
    // Since we only want to cover this case, sample a true value (1) only
    bins covered = {1};
  }
endgroup