用Verilog解决2位BCD加法器输出问题

我正在建立一个2位BCD加法器只使用一个模块。我对verilog比较陌生，所以我不知道我是否在一些作业上犯了错误，但是模拟不会输出任何答案，只要给我输出的X误差就可以了。我不知道我是否在编码模块或编码模拟时出错，但所有波形输出显示的都是输入，但没有输出。我只是想知道我错在哪里了。我被困在这里了

模块的代码如下所示：

   `timescale 1ns / 1ps


module two_digit_BCDAdder(input [7:0] X, input Load, input clk, output [8:0]R );

reg [7:0] Q=0;
always @(posedge clk)
begin 
if (Load)
Q<=X;
else 
Q<=Q;
end 
// 8 bit register 

wire sum1, sum3; 

//wires for both upper  parallel adders sum1 left adder sum 3 right adder

 wire cout1, cout2, cout3, cout4;
// wires for cout,  being cout1 top left adder, cout 2 bottom left adder,
//  cout3 top right adder, cout 4 bottom right adder

 wire cin;
// wire for or gate connected to cin

 wire d1,d2;
// D1 connects or gate of the comparator and cout 1 to PA bottom left,
//  D2 connects or gate of the comparator and cout 1 to PA bottom right,

 wire C1,C2;
// C1 comparator on the left 
// C2 comparator on the right

 assign cin = (cout1|cout2);
// Cin or gate

 assign d1 = (cout1|C1);
 assign d2 =(cout3|C2);
// Creation of or gates

 assign C1 = (sum1 > 4'b1001);
 assign C2= (sum3 > 4'b1001);
// Comparator sum hase tobe greater than 9 for BCD addition

 assign {cout3, sum3}= {Q[0],Q[1],Q[2],Q[3]}+{X[0],X[1],X[2],X[3]};
// Top right Parallel Adder
 assign {cout4,{R[0],R[1],R[2],R[3]}} = sum3+{1'b0,d2,d2,1'b0};
// Bottom left Comparator

 assign {cout1,sum1} = {Q[4],Q[5],Q[6],Q[7]}+{X[4],X[5],X[6],X[7]}+cin;
 // Top left Parallel Adder

 assign {cout2,{R[4],R[5],R[6],R[7]}} = sum1 +{1'b0,d1,d1,1'b0};
 // bottom left Parallel Adder

 assign R[8]=(d1|cout2); 
//or gate for final carry led

endmodule

---

我已经更新了代码，使其模块化。。并添加带有墨迹模块名称的图片

通过上述文件，vivdo模拟器将显示结果

简单代码而不是模块化代码

    module two_digit_BCDAdder(
    input           clk,
    input [7:0]     X,
    input           Load,
    output [8:0]    R
);

reg [7:0] Q = 0;

// 8 bit register
always @(posedge clk)begin
    if (Load) Q <= #10 X;
    else      Q <= #10 Q;
 end

 wire [3:0] AM,AL,BL,BM;
 wire [3:0] sum_PA1,sum_PA2,sum_PA3,sum_PA4;
 wire       cin_PA1,cin_PA2,cin_PA3,cin_PA4;
 wire       cout_PA1,cout_PA2,cout_PA3,cout_PA4;
 wire       or_gate1_out,or_gate2_out,or_gate3_out,or_gate4_out;
 wire       c1_ag9,c2_ag9;

 assign AL = Q[3:0] ;
 assign AM = Q[7:4] ;
 assign BL = X[3:0] ;
 assign BM = X[7:4] ;

 //4 Adders
 assign {cout_PA1,sum_PA1} = AM[3:0] + BM[3:0] + or_gate3_out;
 assign {cout_PA2,sum_PA2} = AL[3:0] + BL[3:0] + 1'b0        ;
 assign {cout_PA3,sum_PA3} = sum_PA1[3:0] + {1'b0,{2{or_gate1_out}},1'b0} + 1'b0;
 assign {cout_PA4,sum_PA4} = sum_PA2[3:0] + {1'b0,{2{or_gate4_out}},1'b0} + 1'b0;

 // 2 Comparators
 assign c1_ag9 = sum_PA1 > 4'h9 ;
 assign c2_ag9 = sum_PA2 > 4'h9 ;

// 4 OR gates
assign or_gate1_out = cout_PA1     || c1_ag9   ;
assign or_gate2_out = or_gate1_out || cout_PA3 ;
assign or_gate3_out = cout_PA2     || cout_PA4 ;
assign or_gate4_out = cout_PA2     || c2_ag9   ;

// Assigning outputs
 assign R[3:0]  = sum_PA4;
 assign R[7:4]  = sum_PA3;
 assign R[8]    = or_gate2_out;

endmodule

---

是否有可能减少模块数量以将其包含在一个模块中，或者这是不可能的。与制造PA加法器或比较器模块类似，有一种方法可以减少这种情况。在vivado Simulator 2019.2和vcs版本O-2018.09-SP2-1中，我尝试了此代码，我能够看到cout_*Rama的切换，我提供的代码的主要问题是什么？是“或门声明”还是“任务”？与简化的代码和那些看起来最耀眼的代码相比，我做的修复似乎给了我一个截短的答案。

     `timescale 1ns / 1ps

module two_digit_BCDAdder(
    input           clk,
    input [7:0]     X,
    input           Load,
    output [8:0]    R
);

reg [7:0] Q = 0;

// 8 bit register
always @(posedge clk)begin
    if (Load) Q <= #10 X;
    else      Q <= #10 Q;
 end

 wire [3:0] AM,AL,BL,BM;
 wire [3:0] sum_PA1,sum_PA2,sum_PA3,sum_PA4;
 wire       cin_PA1,cin_PA2,cin_PA3,cin_PA4;
 wire       cout_PA1,cout_PA2,cout_PA3,cout_PA4;
 wire       or_gate1_out,or_gate2_out,or_gate3_out,or_gate4_out;
 wire       c1_ag9,c2_ag9;

 assign AL = Q[3:0] ;
 assign AM = Q[7:4] ;
 assign BL = X[3:0] ;
 assign BM = X[7:4] ;

adder PA1(
    .a     (AM)
   ,.b     (BM)
   ,.c_in  (or_gate3_out)
   ,.sum   (sum_PA1)
   ,.c_out (cout_PA1)
);

adder PA2(
    .a     (AL)
   ,.b     (BL)
   ,.c_in  (1'b0)
   ,.sum   (sum_PA2)
   ,.c_out (cout_PA2)
);

adder PA3(
    .a     ({1'b0,{2{or_gate1_out}},1'b0})
   ,.b     (sum_PA1)
   ,.c_in  (1'b0)
   ,.sum   (sum_PA3)
   ,.c_out (cout_PA3)
);

adder PA4(
    .a     ({1'b0,{2{or_gate4_out}},1'b0})
   ,.b     (sum_PA2)
   ,.c_in  (1'b0)
   ,.sum   (sum_PA4)
   ,.c_out (cout_PA4)
);

comp C1(
    .a   (sum_PA1)
   ,.ag9 (c1_ag9)
);

comp C2(
    .a   (sum_PA2)
   ,.ag9 (c2_ag9)
);

or_gate or_gate1 (
  .a   (cout_PA1)
 ,.b   (c1_ag9)
 ,.out (or_gate1_out)
);

or_gate or_gate2 (
  .a   (or_gate1_out)
 ,.b   (cout_PA3)
 ,.out (or_gate2_out)
);

or_gate or_gate3 (
  .a   (cout_PA2)
 ,.b   (cout_PA4)
 ,.out (or_gate3_out)
);

or_gate or_gate4 (
  .a   (c2_ag9)
 ,.b   (cout_PA2)
 ,.out (or_gate4_out)
);

 assign R[3:0]  = sum_PA4;
 assign R[7:4]  = sum_PA3;
 assign R[8]    = or_gate2_out;

endmodule

 module adder (input  [3:0] a,b,
               input        c_in,
               output [3:0] sum,
               output       c_out
);
    assign {c_out,sum} = a+b+c_in;
endmodule

module comp (input [3:0] a,
             output      ag9
);
   assign ag9 = a > 4'h9;
endmodule

module or_gate(input  a,b,
               output out
);
    assign out = a||b;
endmodule

     `timescale 1ns / 1ps

module BCD_sim();
reg [7:0]x;
reg b;
reg clk;
wire[8:0]r;

two_digit_BCDAdder dut(
     .clk    (clk)  
    ,.X      (x)
    ,.Load   (b)   
    ,.R      (r)
);

initial
begin 
clk =0;
 forever #1 clk=~clk;
end


initial
 begin 

x=0; b=0;
//Values for test
#2 x=55; b=1;
#2 x=55; b=0;
#4;
#2 x=99; b=1;
#2 x=99; b=0;
#4;
#2 x=87; b=1;
#2 x=78; b=0;
#4;
#2 x=25; b=1;
#2 x=75; b=0;
#4;
#2 x=33; b=1;
#2 x=66; b=0;
#4;
#2 x=69; b=1;
#2 x=96; b=0;



$finish;
end 
endmodule

    module two_digit_BCDAdder(
    input           clk,
    input [7:0]     X,
    input           Load,
    output [8:0]    R
);

reg [7:0] Q = 0;

// 8 bit register
always @(posedge clk)begin
    if (Load) Q <= #10 X;
    else      Q <= #10 Q;
 end

 wire [3:0] AM,AL,BL,BM;
 wire [3:0] sum_PA1,sum_PA2,sum_PA3,sum_PA4;
 wire       cin_PA1,cin_PA2,cin_PA3,cin_PA4;
 wire       cout_PA1,cout_PA2,cout_PA3,cout_PA4;
 wire       or_gate1_out,or_gate2_out,or_gate3_out,or_gate4_out;
 wire       c1_ag9,c2_ag9;

 assign AL = Q[3:0] ;
 assign AM = Q[7:4] ;
 assign BL = X[3:0] ;
 assign BM = X[7:4] ;

 //4 Adders
 assign {cout_PA1,sum_PA1} = AM[3:0] + BM[3:0] + or_gate3_out;
 assign {cout_PA2,sum_PA2} = AL[3:0] + BL[3:0] + 1'b0        ;
 assign {cout_PA3,sum_PA3} = sum_PA1[3:0] + {1'b0,{2{or_gate1_out}},1'b0} + 1'b0;
 assign {cout_PA4,sum_PA4} = sum_PA2[3:0] + {1'b0,{2{or_gate4_out}},1'b0} + 1'b0;

 // 2 Comparators
 assign c1_ag9 = sum_PA1 > 4'h9 ;
 assign c2_ag9 = sum_PA2 > 4'h9 ;

// 4 OR gates
assign or_gate1_out = cout_PA1     || c1_ag9   ;
assign or_gate2_out = or_gate1_out || cout_PA3 ;
assign or_gate3_out = cout_PA2     || cout_PA4 ;
assign or_gate4_out = cout_PA2     || c2_ag9   ;

// Assigning outputs
 assign R[3:0]  = sum_PA4;
 assign R[7:4]  = sum_PA3;
 assign R[8]    = or_gate2_out;

endmodule