Verilog 如何编写多维阵列端口测试台

我有一个用Verilog代码编写的7位向上/向下计数器：

module updowncount_7bit  (clock,reset,hold,up_down,q);
input clock,reset,hold,up_down;
output reg [6:0] q;
integer direction;

    always @(posedge clock)
    begin
        if(up_down)
            direction = 1;
        else
            direction = -1;
        if (!reset)
            q <= 0;                 
        else if (!hold)         
            q <= q + direction;

    end
endmodule

---

您似乎没有从测试台上将

reset

应用到您的模块。因此，

q

将始终是

X

，这看起来就像您看到的一样

module counter_7bit_tb;
  wire [6:0]f_tb;
  reg  clock_in_tb, reset_tb, hold_tb, up_down_tb;
 updowncount_7bit dut(clock_in_tb, reset_tb,hold_tb, up_down_tb, f_tb);


  initial begin
    clock_in_tb = 0;reset_tb= 1; hold_tb = 0;up_down_tb=1;
    #10; 
    forever begin
     #10 clock_in_tb= ~clock_in_tb ;
    end

  end

endmodule