计数器系统verilog代码

我对这个柜台有问题。输出都是xxxxxxxx，我知道我应该将count和overflow的初始值设置为0，但这样会产生错误。代码如下：

// Code your design here
module counter (in, start, count, clk, overflow);

input [3:0] in;
input clk;
input start;
output reg [7:0] count;
output reg overflow;
//reg count;
//count =0;
//overflow=0;
always @ (posedge clk)
  begin
    if (start) begin
      count <= 8'b0;
      overflow <= 1'b0;
    end

    else if (in == 4'b0101) begin
      count <= count+1;
    end
    if (count == 4'b1111) begin
      overflow <=1'b1;
    end
  end

endmodule

---

我知道这是一个简单的问题，但如果你们能帮忙，我会很感激的。

有两个问题需要解决

1） 巧合的是，in=5仅在时钟负边缘期间设置。这是因为clk周期为#10，tb代码每#5更改一次“in”值。当计数器在posedge检查in的值时，它忽略了in=5。 in时间段需要#10，或者TB可以在设置信号“in”之前等待clk的posedge

2） 需要设置start以重置计数器，否则count=x（未知）和count+1=>x+1的值等于x。因此，计数器将不会增加，并始终保持x

更新的tb如下所示

module tb();

  reg [3:0] in;
  reg clk,start;
  wire [7:0] count;
  reg overflow = 1'b0;

  initial begin

    $display ("time\t clk start in count overflow");
    $monitor ("%g\t %b %b %b %b", $time, clk, start, in, count, overflow);

    clk=0;
    in=0;
    start=0;
   // overflow=0;
   // count=0;

    #10 start = 1'b1; // reset counter 
    #10 start = 1'b0;
    #10 in=4'd1;
    #10 in=4'd5;
    #10 in=4'd4;
    #10 in=5'd5;
    #10 in=4'd1;
    #10 in=4'd5;
    #10 in=4'd4;
    #10 in=5'd5;
    #10 in=4'd1;
    #10 in=4'd5;
    #10 in=4'd4;
    #10 in=5'd5;
    #10 in=4'd1;
    #10 in=4'd5;
    #10 in=4'd4;
    #10 in=5'd5;
    #50 $finish;

  end

    always #5 clk=~clk;

  counter u0(.*);

initial  // Dump waveform for debug 
$dumpvars;

endmodule

您可以使用$dumpvars命令转储波形以进行调试

替代代码（使用posedge事件驱动测试台中的数据）

---

计数将保持在X，直到

start

变为1。您遇到了什么错误？是的，您没有通过启动信号重置计数器

module tb();

  reg [3:0] in;
  reg clk,start;
  wire [7:0] count;
  reg overflow = 1'b0;

  initial begin

    $display ("time\t clk start in count overflow");
    $monitor ("%g\t %b %b %b %b", $time, clk, start, in, count, overflow);

    clk=0;
    in=0;
    start=0;
   // overflow=0;
   // count=0;

    #10 start = 1'b1; // reset counter 
    #10 start = 1'b0;
    #10 in=4'd1;
    #10 in=4'd5;
    #10 in=4'd4;
    #10 in=5'd5;
    #10 in=4'd1;
    #10 in=4'd5;
    #10 in=4'd4;
    #10 in=5'd5;
    #10 in=4'd1;
    #10 in=4'd5;
    #10 in=4'd4;
    #10 in=5'd5;
    #10 in=4'd1;
    #10 in=4'd5;
    #10 in=4'd4;
    #10 in=5'd5;
    #50 $finish;

  end

    always #5 clk=~clk;

  counter u0(.*);

initial  // Dump waveform for debug 
$dumpvars;

endmodule

// Code your testbench here
// or browse Examples
module tb();

  reg [3:0] in;
  reg clk,start;
  wire [7:0] count;
  reg overflow = 1'b0;

  initial begin

    $display ("time\t clk start in count overflow");
    $monitor ("%g\t %b %b %b %b", $time, clk, start, in, count, overflow);

    clk=0;
    in=0;
    start=0;
   // overflow=0;
   // count=0;

    @(posedge clk )   start = 1'b1;// reset counter 
    @(posedge clk )   start = 1'b0;
    @(posedge clk )   in=4'd1;
    @(posedge clk )   in=4'd5;
    @(posedge clk )   in=4'd4;
    @(posedge clk )   in=5'd5;
    @(posedge clk )   in=4'd1;
    @(posedge clk )   in=4'd5;
    @(posedge clk )   in=4'd4;
    @(posedge clk )   in=5'd5;
    @(posedge clk )   in=4'd1;
    @(posedge clk )   in=4'd5;
    @(posedge clk )   in=4'd4;
    @(posedge clk )   in=5'd5;
    @(posedge clk )   in=4'd1;
    @(posedge clk )   in=4'd5;
    @(posedge clk )   in=4'd4;
    @(posedge clk )   in=5'd5;
    #50 $finish;

  end

    always #5 clk=~clk;

  counter u0(.*);

initial
$dumpvars;

endmodule