Input Verilog定时和时钟-输入和输出问题

我用verilog写了这段代码，我的代码有问题！ 我想做的是把数字0-127作为输入，这样就可以在mem中写入它们，然后读取它们并查看输出。根据结果，我已经将时钟设置为每5次从0更改为1。但是这些数字在记忆中被重复了不止一次。 我怎样才能解决这个问题，因为数字只能写一次？这可能是计时问题吗

在开始时，输出数据是0，因为我需要先写入数据，然后读取数据

另外，我想知道我需要更改什么，以便当内存的最后一个位置被数字127填充时，我的程序将理解内存中没有其他位置是空的！！ 我正在EDA操场上运行代码

module process_data(
  input wire [63:0] DATA_IN ,  //input data 
  input QUE_Mode,              //fifo or filo 
  //input wire [6:0] AdrR ,    //pointers for read, write
  //input wire [6:0] AdrW,  
  input R_W ,
  input Cen,  
  input clk,
  input reset, 
  output reg [63:0]Reg_Data_Out,  //output data
  output reg Que_Full,            //state of the queue
  output reg Que_Last, 
  output reg Que_Empty);

  integer i;
  reg [63:0] Memory [0:127];      //array 
  reg [6:0] AdrW;
  reg [6:0] AdrR;

  initial begin        //initialization 
   Que_Full= 1'b0;     //when  Que_Full = 1'b0, the queue is not full 
   Que_Last = 1'b0;    //when  Que_Last = 1'b0, this is not the last item of the list that can be added to 
   Que_Empty = 1'b0;   //when Que_Empty = 1'b0, the queue is empty.
   AdrR=7'b0000_000;
   AdrW=7'b0000_000;

   i=0;   
    repeat (128)        //initialization of memory 
    begin
        Memory[i]=64'd1;    //64 bits/ position , 127 positions 
        i=i+1;
    end
   end 

  always @* begin
    $display("AdrR=%d",AdrR);
    $display("AdrW=%d",AdrW);

  end 

  always @(negedge(clk))
  begin
    if(Cen == 1'b1) begin                        // cen = chip enabled , when 1=> chip is enabled => circuit works
    case (R_W)   
      1'b1:
         begin
           if(Que_Empty == 1'b1 )begin           //check if queue not empty
                                                 // Return the value from the FIFO  foun at the read address
              Reg_Data_Out <= Memory[AdrR];      // (read)  out put memory context          
              AdrR<=AdrR+7'b0000_001;            //assign  AdrR [6:0] <= AdrR [6:0] +7'b0000_001;   
           end 
         end 

      1'b0:
        begin 
          if( Que_Full == 1'b0  )begin               //check if queue not full 
            if(AdrW >= 7'b0000_000) begin
              Memory[AdrW] <= DATA_IN ;              // write input to memory , On any write -> update the memory
              AdrW <= AdrW+7'b0000_001;              //non blocking statements to avoid race conditions 
              Que_Empty = 1'b1;                      //when Que_Empty = 1'b1, the queue is NOT empty

              if(AdrW==7'b1111_111)begin  
                                                     //AdrW <= 7'b0000_000;
                 Que_Full= 1'b1;                     //when  Que_Full = 1'b1, the queue IS full 
                 Que_Last = 1'b1;                    //when  Que_Last = 1'b0, this IS the last item of the list that can be added to 
              end 
            end
          end 
        end 

      default:
        Reg_Data_Out = 64'bxxxxxxxx;  
    endcase

    end
  end 
endmodule 


module clock(output reg clk);
  initial
  clk=1'b0;
  always
  #5 clk=~clk;
endmodule


module TOP();
  parameter ENDTIME=40000;  

  reg [63:0] inputdata1;  // is an 63-bit "register", or variable  
  wire [6:0] AddressR,AddressW;

  reg cen, R_W, reset;  //clk=1'b0  , 
  reg QUE_Mode;

  wire [63:0] Data_Out;

  integer count;
  integer i;

  wire Que_Full, Que_Last, Que_Empty;

  wire clk;

  //call module for data I/O 
  process_data process_data(
    inputdata1,
    QUE_Mode,
    //AddressR,
    //AddressW, 
    R_W ,
    cen, 
    clk, 
    reset,
    Data_Out, 
    Que_Full,
    Que_Last,
    Que_Empty);  //reset, Que_Full, Que_Last, Que_Empty do not do anything yet

  clock MyClock(clk);
  initial
  begin
    $dumpfile("ALU.vcd");
    $dumpvars(0);

    $display("\t\t\t\t\t\t\t\t\tSIMULATION RESULT ");  
    $display("\t\ttime\tclk\t\t\tinputdata1\t\tData_Out\tQUE_Mode\t\tAddressR\t\tAddressW\t\tQue_Full\t\Que_Last\t\Que_Empty");
    $monitor($time, "\t%d\t%d\t%d\t%d",clk,inputdata1,Data_Out,QUE_Mode,AddressR,AddressW,Que_Full,Que_Last,Que_Empty);


    cen=1'b1;   //chip enabled 
    count = 0;
    R_W = 1'b0;   //write
    QUE_Mode = 1'b0; // QUE_Mode = 1'b0 => FIFO MODE 
    i=0;

    //input    
    for (i = 0; i < 128; i = i + 1) begin   //input   
                R_W=1'b0;   //write
                inputdata1 = i;
                #20;
           end  

    #10 
    for (i = 0; i < 128; i = i + 1) begin //output   
                #20; 
                R_W=1'b1;   //read  => output
                #20;
           end  
    $display("-------------- THE SIMULATION FINISHED ------------");  
    $finish; 
   end

endmodule

---

您需要以两倍的速度更改输入数据。将

#20

更改为

#10

：

    //input    
    for (i = 0; i < 128; i = i + 1) begin   //input   
                R_W=1'b0;   //write
                inputdata1 = i;
//                #20;
                #10;
           end  

//输入
对于（i=0；i<128；i=i+1）开始//输入
R_W=1'b0//写
输入数据1=i；
//                #20;
#10;
结束

这会将0写入地址0，将1写入地址1。。。127地址127

---

第一次写入是在时间=0时写入地址0。但是，

初始

和

始终

块之间存在竞争条件，这可能导致不同模拟器上的不同行为

---

---

日志文件显示了

clk

的每个边缘上的输出，包括posedge和negedge，因为在

$monitor

语句中有

clk

。但是，数据在每个时钟周期内只改变一次（根据需要）。

看到结果的第一行，其中addrw=1和addrw=2（写入指针），输入是0，然后是0！！！！数字：0作为输入被赋予4次，

    //input    
    for (i = 0; i < 128; i = i + 1) begin   //input   
                R_W=1'b0;   //write
                inputdata1 = i;
//                #20;
                #10;
           end