Process 如何在满足条件后退出灵敏度过程

Process 如何在满足条件后退出灵敏度过程,process,vhdl,conditional-statements,Process,Vhdl,Conditional Statements,我有检查重置或时钟的代码,如果有时钟,它会对“buff”执行一些操作。我想这样做,一旦“buff”等于“key”,它就会退出进程。我怎样才能做到这一点 PROCESS (clock, reset) BEGIN IF(reset = '1') THEN buff <= (others => '0'); -- set buffer to 0 op <= (others =>

我有检查重置或时钟的代码,如果有时钟,它会对“buff”执行一些操作。我想这样做,一旦“buff”等于“key”,它就会退出进程。我怎样才能做到这一点

PROCESS (clock, reset)
        BEGIN
            IF(reset = '1') THEN
                buff <= (others => '0'); -- set buffer to 0
                op <= (others => '0');   -- set output to 0
            ELSIF(clock'EVENT AND clock = '1') THEN
                op <= ip;  --output displays what was inputted
                buff(31 downto 8) <= buff (23 downto 0); --shift least significant 24 bits
                buff(7 downto 0) <= ip; --set empty 8 bits to input
                IF (buff = key) THEN
                    success <= '1';  --once buff = key, output a green light
                ELSE 
                    success <= '0';
                END IF;
            END IF;
    END PROCESS;
过程(时钟、复位)
开始
如果(重置='1'),则
buff“0”);--将缓冲区设置为0
op“0”);--将输出设置为0
ELSIF(时钟事件和时钟='1'),然后

op假设key与buff具有相同的维度,在elsif内部,时钟条件为if语句提供执行需要buff/=key的赋值语句的条件。(比较提供了对寄存器的启用)。