Vhdl 两块FPGA之间的SPI

我正在尝试与SPI通信两个FPGA（SPARTAN 3E初学者套件）。我的主要目的是使用板载ADC和DAC（一个套件的ADC和另一个套件的DAC）实现语音传输系统，但现在，我用电位计给ADC输入提供模拟值，并测量DAC输出。我测试了系统的ADC和DAC部分，它们似乎工作正常。但当我在套件之间添加SPI部件时，我发现了以下问题：

• 当我将代码下载到工具包中时，它们工作不稳定。该系统在多次尝试中成功了几次（当然都是偶然的）

• 为了正确观察板载LED上的数字数据值，我将DAC代码下载到另一个套件时，我发现有时ADC无法工作。（带DAC的套件不可能向另一个套件提供任何数据，但它们似乎相互影响-可能吗？）

• 在我实施设计时，DAC套件上也会收到以下警告：
  位置：1019-已发现时钟IOB/时钟组件对未>放置在最佳时钟IOB/时钟站点对。时钟元件 spi_时钟_BUFGP/BUFG放置在现场BUFGMUX_X1Y10

此外，我使用50MHz时钟

更新：将时钟划分为2MHz频率并没有任何区别

所以，我认为这些问题的原因是我所做的SPI实现，但我不知道它有什么问题。主SPI代码和从SPI代码部分如下所示

大师：

        if(spi_cs = '0') then
                case spistt is
                  when 0 => spi_dataout <= DData(cntrspi) ;
                  when 1 => spi_clock <= '1';
                  when 2 => spi_clock <= '0';
                                if(cntrspi=15) then       
                                    adcstt <= 0;
                                    spi_cs <= '1';
                                end if;
                                cntrspi <= cntrspi +1;
                  when 3 => null;
                end case;
                spistt <= spistt+1; 
            end if;

和.ucf文件：

ADC套件

NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;

NET "Rst" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;

NET "DOUT<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "DOUT<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "DOUT<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "DOUT<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "DOUT<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "DOUT<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "DOUT<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "DOUT<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;


NET "spi_clock" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "spi_dataout" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "spi_cs" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

NET“SPI_SS_B”LOC=“U3”| IOSTANDARD=LVCMOS33 | swil=SLOW | DRIVE=6；
净“SF_CE0”LOC=“D16”| IOSTANDARD=LVCMOS33 | DRIVE=4 | SLOW=SLOW；
NET“FPGA_INIT_B”LOC=“T3”| IOSTANDARD=LVCMOS33 | SLOW=SLOW | DRIVE=4；
净“Rst”LOC=“K17”| IOSTANDARD=LVTTL |下拉；
净“clk”LOC=“C9”| IOSTANDARD=LVCMOS33；
净“SPI_SCK”LOC=“U16”| IOSTANDARD=LVCMOS33 | swil=SLOW | DRIVE=8；
净“AD_CONV”LOC=“P11”| IOSTANDARD=LVCMOS33 | swil=SLOW | DRIVE=6；
净“SPI_MISO”LOC=“N10”| IOSTANDARD=LVCMOS33；
净“DOUT”LOC=“F9”| IOSTANDARD=LVTTL |回转=慢速|驱动=8；
净“DOUT”LOC=“E9”| IOSTANDARD=LVTTL |回转=慢速|驱动=8；
净“DOUT”LOC=“D11”| IOSTANDARD=LVTTL |回转=慢速|驱动=8；
净“DOUT”LOC=“C11”| IOSTANDARD=LVTTL |回转=慢速|驱动=8；
净“DOUT”LOC=“F11”| IOSTANDARD=LVTTL |回转=慢速|驱动=8；
净“DOUT”LOC=“E11”| IOSTANDARD=LVTTL |回转=慢速|驱动=8；
净“DOUT”LOC=“E12”| IOSTANDARD=LVTTL |回转=慢速|驱动=8；
净“DOUT”LOC=“F12”| IOSTANDARD=LVTTL |回转=慢速|驱动=8；
NET“AMP_CS”LOC=“N7”| IOSTANDARD=LVCMOS33 | swil=SLOW | DRIVE=6；
净“SPI_MOSI”LOC=“T4”| IOSTANDARD=LVCMOS33 |回转=慢速|驱动=6；
NET“AMP_SHDN”LOC=“P7”| IOSTANDARD=LVCMOS33 | swil=SLOW | DRIVE=6；
净“spi_clock”LOC=“B4”| IOSTANDARD=LVCMOS33 | swil=FAST | DRIVE=8；
NET“spi_dataout”LOC=“A4”| IOSTANDARD=LVCMOS33 | swil=FAST | DRIVE=8；
NET“spi_cs”LOC=“D5”| IOSTANDARD=LVCMOS33 | swil=FAST | DRIVE=8；

DAC套件：

NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;

NET "Rst" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

NET "spi_clock" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "spi_datain" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "spi_cs" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

NET "spi_clock" CLOCK_DEDICATED_ROUTE=FALSE;


NET "LEDS<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LEDS<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LEDS<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LEDS<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LEDS<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LEDS<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LEDS<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LEDS<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET“SPI_SS_B”LOC=“U3”| IOSTANDARD=LVCMOS33 | swil=SLOW | DRIVE=6；
净“SF_CE0”LOC=“D16”| IOSTANDARD=LVCMOS33 | DRIVE=4 | SLOW=SLOW；
NET“FPGA_INIT_B”LOC=“T3”| IOSTANDARD=LVCMOS33 | SLOW=SLOW | DRIVE=4；
净“Rst”LOC=“K17”| IOSTANDARD=LVTTL |下拉；
净“clk”LOC=“C9”| IOSTANDARD=LVCMOS33；
净“SPI_SCK”LOC=“U16”| IOSTANDARD=LVCMOS33 | swil=SLOW | DRIVE=8；
净“AD_CONV”LOC=“P11”| IOSTANDARD=LVCMOS33 | swil=SLOW | DRIVE=6；
净“DAC_CS”LOC=“N8”| IOSTANDARD=LVCMOS33 |回转=慢速|驱动=8；
NET“DAC_CLR”LOC=“P8”| IOSTANDARD=LVCMOS33 | swil=SLOW | DRIVE=8；
NET“AMP_CS”LOC=“N7”| IOSTANDARD=LVCMOS33 | swil=SLOW | DRIVE=6；
净“SPI_MOSI”LOC=“T4”| IOSTANDARD=LVCMOS33 |回转=慢速|驱动=6；
净“spi_clock”LOC=“B4”| IOSTANDARD=LVCMOS33 | swil=FAST | DRIVE=8；
NET“spi_datain”LOC=“A4”| IOSTANDARD=LVCMOS33 | swil=FAST | DRIVE=8；
NET“spi_cs”LOC=“D5”| IOSTANDARD=LVCMOS33 | swil=FAST | DRIVE=8；
净“spi时钟”时钟专用路径=假；
净“发光二极管”LOC=“F9”| IOSTANDARD=LVTTL |回转=慢速|驱动=8；
净“发光二极管”LOC=“E9”| IOSTANDARD=LVTTL |回转=慢速|驱动=8；
净“发光二极管”LOC=“D11”| IOSTANDARD=LVTTL |回转=慢速|驱动=8；
净“发光二极管”LOC=“C11”| IOSTANDARD=LVTTL |回转=慢速|驱动=8；
净“发光二极管”LOC=“F11”| IOSTANDARD=LVTTL |回转=慢速|驱动=8；
净“发光二极管”LOC=“E11”| IOSTANDARD=LVTTL |回转=慢速|驱动=8；
净“发光二极管”LOC=“E12”| IOSTANDARD=LVTTL |转换=慢速|驱动=8；
净“发光二极管”LOC=“F12”| IOSTANDARD=LVTTL |回转=慢速|驱动=8；

这有什么问题？或者我应该完全改变算法吗？我的时间不多了，所以任何帮助都将不胜感激。

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谢谢。

查看Xilinx的答案记录

确保已将SPI时钟信号放置在正确的引脚上，并在约束文件中将其定义为时钟

请尽量不要在你的设计中使用时钟的下降沿

---

我建议使用您的50MHz时钟将所有数据同步到您的块中，然后使用SPIC_CLK作为控制状态机的信号，这样您设计中的所有信号都与同一时钟同步，并且您消除了SPI通信中的任何噪声

您运行的频率是多少？您需要提供更多信息，请提供信号的约束条件，这将有助于更好地理解问题。另外，从您的灵敏度列表中删除spi_数据输入，这不是必需的，也是错误的。帮助您的一件事是查看代码的RTL示意图，看看它是否按照您希望的方式实现了设计

NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;

NET "Rst" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;

NET "DOUT<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "DOUT<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "DOUT<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "DOUT<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "DOUT<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "DOUT<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "DOUT<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "DOUT<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;


NET "spi_clock" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "spi_dataout" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "spi_cs" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;

NET "Rst" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

NET "spi_clock" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "spi_datain" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "spi_cs" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

NET "spi_clock" CLOCK_DEDICATED_ROUTE=FALSE;


NET "LEDS<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LEDS<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LEDS<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LEDS<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LEDS<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LEDS<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LEDS<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LEDS<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;