System verilog 无法编译我的UVM类
我有两个文件sequence_item.sv和sequencer.sv，分别包含以下内容。我无法编译sequencer.sv，出现错误System verilog 无法编译我的UVM类,system-verilog,uvm,System Verilog,Uvm,我有两个文件sequence_item.sv和sequencer.sv，分别包含以下内容。我无法编译sequencer.sv，出现错误 ** Error: /afs/asu.edu/users/s/m/u/smukerji/UVM_practice/sequencer.sv(6): (vlog-2730) Undefined variable: 'Packet'. 也许这是一个简单的错误。我的两个班是 //Sequence item import uvm_pkg::*; `include "u
** Error: /afs/asu.edu/users/s/m/u/smukerji/UVM_practice/sequencer.sv(6): (vlog-2730) Undefined variable: 'Packet'.
//Sequence item
import uvm_pkg::*;
`include "uvm_macros.svh"
class Packet extends uvm_sequence_item;
typedef enum bit [1:0] {NO_ERROR, SINGLE_ERROR, DOUBLE_ERROR, MULTIPLE_ERROR} err_type;
rand logic [127:0] correct_data_in;
rand logic valid_in;
logic [136:0] corrupted_data_in;
rand logic corrupt_valid_in;
rand bit error;
rand bit [127:0] err_pos;
randc err_type error_type;
logic [136:0] corrupt_data;
constraint type_of_error { (error == 0) -> error_type == NO_ERROR; }
constraint error_sequence {
if (error_type == SINGLE_ERROR) $countones(err_pos) inside {0,1};
else if (error_type == DOUBLE_ERROR) $countones(err_pos) inside {1,2};
else if (error_type == MULTIPLE_ERROR) $countones(err_pos) inside {2,127};
else err_pos inside {0, 0};
}
`uvm_object_utils_begin(Packet)
`uvm_field_enum(err_type, error_type, UVM_ALL_ON)
`uvm_field_int(correct_data_in, UVM_ALL_ON|UVM_NOPACK)
`uvm_field_int(valid_in, UVM_ALL_ON|UVM_NOPACK)
`uvm_field_int(corrupted_data_in, UVM_ALL_ON|UVM_NOPACK)
`uvm_field_int(corrupt_valid_in, UVM_ALL_ON|UVM_NOPACK)
`uvm_field_int(error, UVM_ALL_ON)
`uvm_field_int(err_pos, UVM_ALL_ON)
`uvm_object_utils_end
function new(string name="Packet");
super.new(name);
endfunction
function logic [136:0] create_corrupt_data;
logic [136:0] corrupt_data;
corrupt_data = err_pos ^ correct_data_in;
return corrupt_data;
endfunction
//virtual function void do_pack (uvm_packer packer);
//super.do_pack(packer);
//`uvm_pack_int(correct_data_in);
//`uvm_pack_int(valid_in);
//`uvm_pack_int(corrupted_data_in);
//`uvm_pack_int(corrupt_valid_in);
//packer.pack_field_int(correct_data_in,$bits(correct_data_in));
//packer.pack_field_int(valid_in,$bits(valid_in));
//packer.pack_field_int(corrupted_data_in,$bits(corrupted_data_in));
//packer.pack_field_int(corrupt_valid_in,$bits(corrupt_valid_in));
//endfunction
//virtual function void do_unpack (uvm_packer packer );
//super.do_unpack(packer);
//correct_data_in = packer.unpack_field_int($bits(correct_data_in));
//valid_in = packer.unpack_field_int($bits(valid_in));
//corrupted_data_in = packer.unpack_field_int($bits(corrupted_data_in));
//corrupt_valid_in = packer.unpack_field_int($bits(corrupt_valid_in));
//endfunction
endclass
//Sequencer
import uvm_pkg::*;
`include "uvm_macros.svh"
typedef uvm_sequencer #(Packet) packet_sequencer;
您很可能在单独的文件中分别编译了这两个代码类。在一个编译单元中编译的代码对另一个编译单元不可见。您应该将类编译到一个包中
package my_stuff;
`include "Packet.svh"
`include "packet_sequencer.svh"
endpackage
您很可能在单独的文件中分别编译了这两个代码类。在一个编译单元中编译的代码对另一个编译单元不可见。您应该将类编译到一个包中
package my_stuff;
`include "Packet.svh"
`include "packet_sequencer.svh"
endpackage
那么您是说在包中包含所有类作为class_name.svh，然后在所有文件中包含并导入包？另外，对我来说，sequencer不是一个类是的，你可以在使用这些类的文件中导入包。您可以将
typedeftypedef