Verilog BASYS 2中的查询注册表.ucf文件

我想在BASYS2板的七段显示屏上滚动hello world。我已经创建了这个.ucf文件，我想知道是否必须在.ucf中包含时钟和重置管脚。我的.ucf文件和verilog代码如下：

module ssevenseg (
input clock, 
input reset, 
output a,
output b,
output c,
output d,
output e,
output f,
output g,
output [3:0] en
); 
reg [3:0] in0, in1, in2, in3;  // 
reg [28:0] tick_tock;  // to count for every 1s i.e holds count of 50 M
wire click; 


always @(posedge clock or posedge reset)
begin
if(reset)
tick_tock <= 0;
else if ( tick_tock==50000000)
tick_tock <= 0;
else
tick_tock <= tick_tock+1;
end

assign click = (( tick_tock==50000000)?1’b1:1’b0);  // click every second
reg [3:0] count1;  
always @(posedge click or posedge reset)
begin 
if (reset)
count1 <= 0;
else
count1 <= count1 + 1;
end



always @ (*)
begin
case (count1)
8’b00000000 :
begin
in0 = 4’b0001;  // H
in1 = 4’b0010;  // E
in2 = 4’b0011;  // L
in3 = 4’b0011;  // L
end
8’b00000001 :
begin
in0 = 4’b0010;  // E
in1 = 4’b0011;  // L
in2 = 4’b0011;  // L
in3 = 4’b0100;  // O
end
8’b00000010 :
begin
in0 = 4’b0011;  // L
in1 = 4’b0011;  // L
in2 = 4’b0100;  // O
in3 = 4’b0101;  // E
end
8’b00000011 :
begin
in0 = 4’b0011; // L
in1 = 4’b0100;  // O
in2 = 4’b0101;  // E
in3 = 4’b0100;  // O
end
8’b00000100 :
begin
in0 = 4’b0100;  // O
in1 = 4’b0101;  // E
in2 = 4’b0100;  // O
in3 = 4’b0110;  // r
end
8’b00000101 :
begin
in0 = 4’b0101;  // E
in1 = 4’b0100;  // O
in2 = 4’b0110;   // r
in3 = 4’b0011;  // L
end
8’b00000110 :
begin
in0 = 4’b0100;
in1 = 4’b0110;
in2 = 4’b0011;
in3 = 4’b0111;
end
endcase
end


localparam N = 18;

reg [N-1:0]count;  // the 18 bit counter that allows us to multiplex at 1000Hz

count <= 0;
always @ (posedge clock or posedge reset )
begin
if (reset)
count <= 0;
else
count <= count +1;
end

reg [3:0] display;
reg [3:0] temp_en;

always @ (*)
begin
case(count[N-1:N-2])    

2'b00 : 
    begin
    display = in0;
    temp_en = 4'b0111;  
    end

2'b01: 
     begin 
     display = in1;
     temp_en = 4'b1011;
     end

   2'b10: 
    begin
    display = in2;
    temp_en = 4'b1101;
    end

   2'b11:  
    begin
    display = in3;
    temp_en = 4'b1110;
    end
  endcase
 end   // end of begin

assign en = temp_en;


reg [6:0] temp_display;



always @(*)
begin

case (display)

4’b0000 : temp_display = 7’b1111110;  // if we give input ‘0’ nothing except ‘-‘ will be displayed
4’b0001 : temp_display = 7’b1001000;  // This will display ‘H’
4’b0010 : temp_display = 7’b0110000;  // to display ‘E’
4’b0011 : temp_display = 7’b1110001; // to display ‘L’
4’b0100 : temp_display = 7’b0000001; // to display ‘O’
4’b0101 : temp_display = 7’b1111010; // to display ‘r’
4’b0110 : temp_display = 7’b1000010; // to display ‘d’

default : temp_display = 7’b1111111; // blank

endcase
end
 assign {a,b,c,d,e,f,g} = temp_display ; 
endmodule




.UCF FILE :

NET a LOC = "L14";
NET b LOC = "H12";
NET c LOC = "N14";
NET d LOC = "N11";
NET e LOC = "P12";
NET f LOC = "L13";
NET g LOC = "M12";
NET en[3] LOC = "F12";
NET en[2] LOC = "J12";
NET en[1] LOC = "M13";
NET en[0] LOC = "K14";

模块ssevenseg(
输入时钟，
输入复位，
输出a，
产出b，
产出c，
产出d，
产出e，
产出f，
产出g，
输出[3:0]en
); 
reg[3:0]in0，in1，in2，in3；//
reg[28:0]勾选每1秒计数，即保持50米计数
线击；
始终@（posedge时钟或posedge重置）
开始
如果（重置）
勾选按钮是，您必须将它们添加到ucf文件中，否则位置和路线将不知道这些信号必须链接到哪个引脚上

您也可以在ucf中这样定义时钟周期约束（对于1MHz时钟）：

仅供参考，您需要将默认案例添加到第一个
始终@（*）
，即带有
案例（count1）
的案例。目前这个案例还不完整，因此您推断出复杂的锁存逻辑，它将占用巨大的面积，并且具有可怕的时间
in0
到
in3
需要在always块中的每个可能分支中分配一个确定值。
NET "clock" TNM_NET = TNM_clock;
TIMESPEC "TS_clock" = PERIOD "TNM_clock" 1 us;