Verilog 有没有办法让我知道我的错误在哪里?

Verilog 有没有办法让我知道我的错误在哪里?,verilog,Verilog,我试图创建Verilog代码,然后在Hneemann的Digital上生成秒表,但我遇到了一些错误。没有迹象表明我的错误在哪里,所以我无法确定在哪里可以找到它们。我将在下面发布代码,看看是否有人能发现它 module cronometro( input clk, input rst, input [6:0] minuto, input start, output [6:0] m1, output [6:0] m2, output [6:0

我试图创建Verilog代码,然后在Hneemann的Digital上生成秒表,但我遇到了一些错误。没有迹象表明我的错误在哪里,所以我无法确定在哪里可以找到它们。我将在下面发布代码,看看是否有人能发现它

module cronometro(

    input clk,
    input rst,
    input [6:0] minuto,
    input start,
    output [6:0] m1,
    output [6:0] m2,
    output [6:0] s3,
    output [6:0] s4

);

parameter q0 = 3'd0,  q1 = 3'd1, q2 = 3'd2, q3 = 3'd3, q4 = 3'd4, q5 = 3'd5;

    reg [7:0] a, b, n;
    reg [7:0] snA, snB, snN;
    reg [2:0] cs, ns;

    

always @(*)
begin
   case(cs)

            q0: ns = q1; 
            q1: ns = a!= n? q2:q6;
            q2: ns = q3;
            q3: ns = b!=8'd60? q2:q4;
            q4:ns = q1;
            q5: ns = q5;
            default: begin
                ns = q0; 
            end
    endcase

         always @(posedge clk) begin
        if(rst)
            cs <= q0;
        else 
            cs <= ns;
        end

    always @(posedge clk) begin
        a <= snA;
        b <= snB;
    end

 always @(*) begin

        if (enabled) begin
        case(cs)

            q0: begin
                snA = 8'd0;  
                snB = 8'd0;  
                snN = minuto;            
            end

            q1: begin
                snA = a;  
                snB = b;  
                snN = minuto; 
            end
            
            q2: begin
                snA = a;  
                snB = b + 8'd1; 
                snN = minuto;  
            end
            
            q3: begin
                snA = a;  
                snB = b;  
                snN = minuto; 
            end
            
            q4: begin
                snA = a + 8'd1;  
                snB = 8'd0;  
                snN = minuto; 
            end
            
            q5: begin
                snA = a;  
                snB = b; 
                snN = minuto;  
            end
            

            default: begin
                snA = 8'd0;  
                snB = 8'd0; 
                snN = minuto;
            end
        endcase 
        end
    end

end

endmodule
cronometro模块(
输入时钟,
输入rst,
输入[6:0]分钟,
输入启动,
输出[6:0]m1,
输出[6:0]平方米,
输出[6:0]s3,
输出[6:0]s4
);
参数q0=3'd0,q1=3'd1,q2=3'd2,q3=3'd3,q4=3'd4,q5=3'd5;
注册号[7:0]a,b,n;
注册[7:0]snA、snB、snN;
注册号[2:0]cs,ns;
始终@(*)
开始
个案(政务司司长)
q0:ns=q1;
q1:ns=a!=Nq2:q6;
q2:ns=q3;
问题3:ns=b=8点60分?第二季度:第四季度;
q4:ns=q1;
q5:ns=q5;
默认值:开始
ns=q0;
结束
尾声
始终@(posedge clk)开始
如果(rst)

cs由于以下原因,我出现了几个编译错误:

  • 缩进不一致导致开始/结束不匹配
  • 未声明的信号:
    已启用
    q6
  • 运算符周围缺少空格
当您不理解错误消息时,请在其他模拟器上尝试您的代码,例如上的模拟器

这段代码对我来说编译时没有错误:

module cronometro(

    input clk,
    input rst,
    input [6:0] minuto,
    input start,
    output [6:0] m1,
    output [6:0] m2,
    output [6:0] s3,
    output [6:0] s4

);

parameter q0 = 3'd0,  q1 = 3'd1, q2 = 3'd2, q3 = 3'd3, q4 = 3'd4, q5 = 3'd5;

    reg [7:0] a, b, n;
    reg [7:0] snA, snB, snN;
    reg [2:0] cs, ns;

reg enabled, q6;

always @(*)
begin
   case(cs)

            q0: ns = q1; 
            q1: ns = a != n ? q2 : q6;
            q2: ns = q3;
            q3: ns = b != 8'd60 ? q2 : q4;
            q4:ns = q1;
            q5: ns = q5;
            default: begin
                ns = q0; 
            end
    endcase
end

always @(posedge clk) begin
        if(rst)
            cs <= q0;
        else 
            cs <= ns;
end

always @(posedge clk) begin
    a <= snA;
    b <= snB;
end

always @(*) begin

        if (enabled) begin
        case(cs)

            q0: begin
                snA = 8'd0;  
                snB = 8'd0;  
                snN = minuto;            
            end

            q1: begin
                snA = a;  
                snB = b;  
                snN = minuto; 
            end
            
            q2: begin
                snA = a;  
                snB = b + 8'd1; 
                snN = minuto;  
            end
            
            q3: begin
                snA = a;  
                snB = b;  
                snN = minuto; 
            end
            
            q4: begin
                snA = a + 8'd1;  
                snB = 8'd0;  
                snN = minuto; 
            end
            
            q5: begin
                snA = a;  
                snB = b; 
                snN = minuto;  
            end
            

            default: begin
                snA = 8'd0;  
                snB = 8'd0; 
                snN = minuto;
            end
        endcase 
        end
end

endmodule
cronometro模块(
输入时钟,
输入rst,
输入[6:0]分钟,
输入启动,
输出[6:0]m1,
输出[6:0]平方米,
输出[6:0]s3,
输出[6:0]s4
);
参数q0=3'd0,q1=3'd1,q2=3'd2,q3=3'd3,q4=3'd4,q5=3'd5;
注册号[7:0]a,b,n;
注册[7:0]snA、snB、snN;
注册号[2:0]cs,ns;
reg已启用,q6;
始终@(*)
开始
个案(政务司司长)
q0:ns=q1;
q1:ns=a!=Nq2:q6;
q2:ns=q3;
问题3:ns=b!=8点60分?第二季度:第四季度;
q4:ns=q1;
q5:ns=q5;
默认值:开始
ns=q0;
结束
尾声
结束
始终@(posedge clk)开始
如果(rst)
反恐精英