Verilog 模块实例化时使用；“数字符号”；

我有带FIFO的主模块。
这是：

module syn_fifo #(
    parameter DATA_WIDTH = 8,   // inpit capacity
    parameter DATA_DEPTH = 8    // the depth of the FIFO
)
(
    input wire clk,
    input wire rst,
// Write_______________________________________________
    input wire [DATA_WIDTH-1:0]din,     // the input data
    input wire wren,                    // Write anable
    output wire full,
// Read________________________________________________
    output wire [DATA_WIDTH-1:0]dout,   // The output data
    input wire rden,                    // Read enable
    output wire empty
);  
    
integer q_size;         // The queue size(length)
integer golova;         // The queue beginning
integer hvost;          // The end of queue

reg [DATA_WIDTH-1:0]fifo[DATA_DEPTH-1:0];

assign full = (q_size == DATA_DEPTH) ? 1'b1: 1'b0;          // FIFO is full
/*
True { full = (q_size==DATA_TEPTH) = 1 }, then wire "full" goes to "1" value
False { full = (q_size==DATA_TEPTH) = 0 }, then wire "full" goes to "0" value
*/
assign empty = (golova == hvost);                           // FIFO is empty
assign dout = fifo[hvost];                                  // FWFT (other write mode)

integer i;

//___________(The queue fullness)___________________
always @(posedge clk or posedge rst)
begin

    if (rst == 1'b1)
        begin
            for (i = 0; i < DATA_DEPTH; i = i + 1)              // incrementing the FIFO
                fifo[i] <= 0;                                   // Resetting the FIFO
                golova <= 0;                                    // Resetting the queue start variable
        end 
    
    else
    
    begin       //Write_______________________________________
    if (wren && ~full)
        begin
            fifo[golova] <= din;                    // putting data in to the golova
                if (golova == DATA_DEPTH-1)         // restrictions for the queue beginning
                    golova <= 0;                    // Reset the beginning
                else
                golova <= golova + 1;               // other occurence incrementing
        end 
    end
end
//Reading
always @(posedge clk or posedge rst)
begin
        if (rst == 1'b1)
            begin
                hvost <= 0;
            end

        else
            begin
                if (rden && !empty)
    /*for staying inside the queue limits - make the check of non equality of the "hvost" & "queue size"*/              
                    begin
                        if (hvost == DATA_DEPTH-1)              // if hvost = DATA_DEPTH-1, then
                            hvost <= 0;                         // Reset hvost
                        else
                            hvost <= hvost + 1;
                    end
            end
end



always @ (posedge clk) 

    begin
        if (rst == 1'b1) begin
            q_size <= 0;
        end 
    
    else 
        begin
            case ({wren && ~full, rden && ~empty} )
                2'b01: q_size <= q_size + 1;    // RO
                2'b10: q_size <= q_size - 1;    // WO
                default: q_size <= q_size;      // read and write at the same time
            endcase     
        end
end

endmodule

在必要的“138”行，模块实例化中的“数字符号”可能涵盖了主要错误

/*132|*/            initial begin
/*133|*/                        $dumpfile("test.vcd");
/*134|*/                        $dumpvars(0,fifo_tb);   
/*135|*/                    end
/*136|*/
/*137|*/            syn_fifo #(.DATA_WIDTH(DATA_WIDTH),
/*138|*/                       .DATA_DEPTH(DATA_DEPTH))  dut (  .clk(clk),
/*139|*/                                                        .rst(rst),
/*140|*/                                                        .din(din),
/*141|*/                                                        .wren(wren),
/*142|*/                                                        .full(full),
/*143|*/                                                        .dout(dout),
/*144|*/                                                        .rden(rden),
/*145|*/                                                        .empty(empty));
/*146|*/
/*147|*/            endmodule 

---

我不是舒尔那样的人。

似乎您要将fifo.v指定为您的输出文件，请尝试：

iverilog -o syn_fifo.tb -s fifo_tb fifo_tb.v fifo.v

-o -> output file
-s -> top module (in this case, the test one)
(after everything, include all the files)

然后，要运行它：

vvp syn_fifo.tb

---

谢谢你，亲爱的@m4j0rt0m！我只是忘了在CMD窗口中输入输出文件名。我非常疲惫，所以没有注意到这样一个细节。）通常它看起来像：

iverilog-o输出文件\u名称fifo\u tb.v fifo.v

，我也尝试了你的建议，终于完成了！

iverilog -o syn_fifo.tb -s fifo_tb fifo_tb.v fifo.v

-o -> output file
-s -> top module (in this case, the test one)
(after everything, include all the files)

vvp syn_fifo.tb