verilog testbench-在文件中写入子模块阵列_Verilog_Object Test Bench

verilog testbench-在文件中写入子模块阵列

verilog

verilog testbench-在文件中写入子模块阵列,verilog,object-test-bench,Verilog,Object Test Bench,我需要在verilog测试台的文件中写入一个数组。该数组在所附的模块stage1.v层次结构图中声明如下 wire [WIDTH-1:0] s1_res1_arr[0:LENGTH-1]; 它充满了某些值在我的测试台上，我是这样写的 write_file = $fopen("stage1.txt"); for ( i = 0 ; i <= 255 ; i = i+1 ) $fwrite(write_file,"%b \n",FFT_top/stage1/s1_res1_arr[

我需要在verilog测试台的文件中写入一个数组。该数组在所附的模块stage1.v层次结构图中声明如下

wire [WIDTH-1:0] s1_res1_arr[0:LENGTH-1];

它充满了某些值

在我的测试台上，我是这样写的

write_file = $fopen("stage1.txt"); 

for ( i = 0 ; i <= 255 ; i = i+1 )
  $fwrite(write_file,"%b \n",FFT_top/stage1/s1_res1_arr[i]);

好的，我自己找到的。将按以下方式进行：

$fwrite(write_file1,"%b \n",uut.FFT_top.stage_1.s1_res1_arr[i]);

$fwrite(write_file1,"%b \n",uut.FFT_top.stage_1.s1_res1_arr[i]);