verilog声明非有线
试图声明一条导线与导线C相反，我们使用nC表示该导线verilog声明非有线,verilog,iverilog,Verilog,Iverilog,试图声明一条导线与导线C相反，我们使用nC表示该导线 module lab_4 (A,B,C,D,E,Y); output Y; input A; input B; input C; input D; input E; wire A; wire B; wire C; wire D; wire E; wire nA; wire nB; wire nC; wire nD; wire nCE; wire nAnCE; wire nABD; wire nBnDE; wire
module lab_4 (A,B,C,D,E,Y);
output Y;
input A;
input B;
input C;
input D;
input E;
wire A;
wire B;
wire C;
wire D;
wire E;
wire nA;
wire nB;
wire nC;
wire nD;
wire nCE;
wire nAnCE;
wire nABD;
wire nBnDE;
wire ACnD;
wire Y;
assign nA = ~A;
assign nB = ~B;
assign nC = ~C;
assign nD = ~D;
or (nCE,nC,E);
and (nAnCE,nA,nCE);
and (nABD,nA,B, D);
and (nBnDE, nB, nD, E);
and (ACnD, A, C, nD);
or (Y,nAnCE, nABD, nBnDE, ACnD);
endmodule