verilog ripple alu。。slt操作得到“x”

我想用一个比特的alu创建一个ripple alu

除了slt操作外，一切正常

它是这样实现的，对于一位alu，输入“更少”

它被设置为零，除了LSB，它的值来自减法运算的MSB

one_bit_alu alu0 (.op(op), .a(a[0]), .b(b[0]), .cin(1'b0 ),    .less(set),  .r(z[0]), .cout(carry[0]));               
one_bit_alu alu1 (.op(op), .a(a[1]), .b(b[1]), .cin(carry[0]), .less(1'b0), .r(z[1]), .cout(carry[1]));
one_bit_alu alu2 (.op(op), .a(a[2]), .b(b[2]), .cin(carry[1]), .less(1'b0), .r(z[2]), .cout(carry[2]));
one_bit_alu alu3 (.op(op), .a(a[3]), .b(b[3]), .cin(carry[2]), .less(1'b0), .r(z[3]), .cout(carry[3]));
one_bit_alu alu4 (.op(op), .a(a[4]), .b(b[4]), .cin(carry[3]), .less(1'b0), .r(z[4]), .cout(carry[4]));
one_bit_alu alu5 (.op(op), .a(a[5]), .b(b[5]), .cin(carry[4]), .less(1'b0), .r(z[5]), .cout(carry[5]));
one_bit_alu alu6 (.op(op), .a(a[6]), .b(b[6]), .cin(carry[5]), .less(1'b0), .r(z[6]), .cout(carry[6]));
one_bit_alu alu7 (.op(op), .a(a[7]), .b(b[7]), .cin(carry[6]), .less(1'b0), .r(z[7]), .set(set));

以下是一位alu模块中“设置”信号的逻辑

full_subtractor  subtract(.d(subOP), .a(b), .b(a), .Bor_in(cin), .Bor_out(subOP_bout));
and (set, subOP, 1'b1);

似乎一切都很好，但我得到的是“x”

================================= 一位alu模块

`include "../lib/mux_16to1.v"
`include "../lib/full_adder.v"
`include "../lib/full_subtractor.v"

module one_bit_alu (
  input  [3:0] op,
  input  a, b, cin, less, sub,
  output r, cout, bout, set
  );

wire int0, int1, int2, int3, addOP, subOP, addOP_cout, subOP_bout;
and (int0 , a, b);
or  (int1  , a, b);
xor (int2 , a, b);
nor (int3, a, b);

xor (xorB, b, sub);

full_adder       add     (.sum(addOP), .a(a), .b(b), .cin(cin), .cout(addOP_cout));
full_subtractor  subtract(.d  (subOP), .a(b), .b(a), .Bor_in(cin), .Bor_out(subOP_bout));

and (set, subOP, 1'b1);

mux_16to1 mux0(
  .s  (op   ),
  .i0 (int0 ),
  .i1 (int1 ),
  .i2 (addOP),
  .i6 (subOP),
  .i7 (less ),
  .i12(int3 ),
  .z  (r    )
);

mux_16to1 mux1(
  .s(op),
  .i2(addOP_cout),
  .i6(subOP_bout),
  .z(cout));
endmodule

全减法器模块

module full_subtractor (
  output Bor_out, d,
  input a, b, Bor_in
  );

wire int1, int2, int3, int4, b_bar;

// d = (a xor b) xor Bor_in
xor (int1, a, b);
xor (d, int1, Bor_in);

// Bor_out = ((a xor b)' and Bor_in) or (a and b')
not (int2, int1);
and (int3, int2, Bor_in); //(a xor b)' and Bor_in
not (b_bar, b);
and (int4, b_bar, a); //a and b'
or  (Bor_out, int4, int3);

endmodule

找到了

stl运算依赖于减法运算，在我的设计中，我为cout制作了一个mux，根据“op”的不同，从加法器或减法器中获取，因此我应该根据需要输出stl运算， mux1将是这样的

mux_16to1 mux1(
  .s(op),
  .i2(addOP_cout),
  .i6(subOP_bout),
  .i7(subOP_bout), //2 days to find this line!
  .z(cout));

---

这将有助于提供一个完整的、经过提炼的示例，其中至少包含诸如一位alu和全减法器等模块的定义以及周围的接线声明。