If语句Verilog中的多个条件

我有以下if/else声明：

if ((write1 && write 2) && ( read_reg1== read_reg2))
      reg_file[write_reg1] =  write_data1;
    else if((write1 && write 2) && ( read_reg1!=read_reg2)) begin 
      reg_file[write_reg2] =  write_data2;
      reg_file[write_reg1] =  write_data1;
    end
    else if (write1)
      reg_file[write_reg1] =  write_data1;
    else 
      reg_file[write_reg2] =  write_data2;

我发现以下错误：

ERROR VCP2000 "Syntax error. Unexpected token: 2[_UNSIGNED_NUMBER]. Expected tokens: '[' , '(*' , '(' , 'with' , '++' ... ." "design.sv" 23  28
ERROR VCP2000 "Syntax error. Unexpected token: ). Expected tokens: '(*' , '++' , '--'." "design.sv" 23  58
ERROR VCP2000 "Syntax error. Unexpected token: 2[_UNSIGNED_NUMBER]. Expected tokens: '[' , '(*' , '(' , 'with' , '++' ... ." "design.sv" 25  31
ERROR VCP2000 "Syntax error. Unexpected token: ). Expected tokens: '(*' , '++' , '--'." "design.sv" 25  60
ERROR VCP2000 "Syntax error. Unexpected token: else[_ELSE]. Expected tokens: '#' , ''' , '(' , ';' , '@' ... ." "design.sv" 29  9

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那么这里的问题是什么呢？

变量名中有一个空格

write 2

应该是

write2

注意：这种情况发生两次-在“if”和第一个“else if”中