在Verilog中签名扩展器,给出don';你不在乎吗?
代码: 试验台:在Verilog中签名扩展器,给出don';你不在乎吗?,verilog,modelsim,Verilog,Modelsim,代码: 试验台: module signextend(input wire [15:0] inputVal, output wire [31:0] outputVal); assign outputVal = {{16{inputVal[15]}}, inputVal}; endmodule 输出: module lastname_SignExt; reg [15:0] input1; wire [31:0] output1; signextend
module signextend(input wire [15:0] inputVal, output wire [31:0] outputVal);
assign outputVal = {{16{inputVal[15]}}, inputVal};
endmodule
输出:
module lastname_SignExt;
reg [15:0] input1;
wire [31:0] output1;
signextend mySignExt(input1, output1);
initial begin
#350
$dumpfile("lastname_SignExt.vcd");
$dumpvars(350, lastname_SignExt);
$display("***********Sign Extender Test***********\n");
input1 = 16'b0000000000000110;
$display("input1 %16b extended: output1 %32b", input1,output1);
//if(output1 == 32'hFFFF1000)
// $display("Sign Extender Test 1 Passed, Input was %d and Ouput is %d!\n", input1, output1);
//else
// $display("Sign Extender Test 1 Failed!\n");
// #50
// input1 = 16'h0001;
// if(output1 == 32'h00000001)
// $display("Sign Extender Test 1 Passed, Input was %d and Ouput is %d!\n", input1, output1);
// else
// $display("Sign Extender Test 2 Failed!\n");
$finish;
end
endmodule
当我在
$display
之前添加延迟时,我在output1
中不再看到未知位(x
):
VCD info: dumpfile lastname_SignExt.vcd opened for output.
***********Sign Extender Test***********
input1 0000000000000110 extended: output1 xxxxxxxxxxxxxxxx0000000000000110
输出:
input1 = 16'b0000000000000110;
#1;
$display("input1 %16b extended: output1 %32b", input1,output1);
最好在信号值稳定时,而不是在变化时,
$显示信号值。这是否回答了您的问题?
***********Sign Extender Test***********
input1 0000000000000110 extended: output1 00000000000000000000000000000110