Verilog模拟错误。Modelsim Altera 10.1b
这是我4位全加器的门级代码Verilog模拟错误。Modelsim Altera 10.1b,verilog,Verilog,这是我4位全加器的门级代码 //Define stimulus module stimulus; //setup variables reg[3:0] A,B; reg C_IN; wire [3:0] SUM; wire C_OUT; //Instantiate 4 bi full adder fulladd4 FA1_4(SUM,C_OUT,A,B,C_IN); //Setup for monitoring the values initial begin
//Define stimulus
module stimulus;
//setup variables
reg[3:0] A,B;
reg C_IN;
wire [3:0] SUM;
wire C_OUT;
//Instantiate 4 bi full adder
fulladd4 FA1_4(SUM,C_OUT,A,B,C_IN);
//Setup for monitoring the values
initial
begin
$monitor($time," A= %b,B= %b,C_IN= %b, --- C_OUT= %b, SUM= %b \n",A,B,C_IN,C_OUT,SUM);
end
//Stimulate Inputs
initial
begin
A = 4'd0; B = 4'd0; C_IN = 1'b0;
#5 A = 4'd1; B = 4'd2;
#5 A = 4'd3; B = 4'd4;
end
endmodule
//Define full 1 bit adder
module fulladd(sum, c_out,a,b,c_in);
//I/O Ports Declaration
output sum,c_out;
input a,b,c_in;
//Internal nets
wire s1, c1, s2;
//Instantating the gates
xor (s1,a,b);
and (c1,a,b);
xor (sum,s1,c_in);
and (s2,s1,c_in);
xor (c_out,s2,c1);
endmodule
//Define a 4 bit full adder
module fulladd4(sum,c_out,a,b,c_in);
//I/O Ports declaration
output [3:0] sum;
output c_out;
input [3:0] a,b;
input c_in;
//internal nets
wire c1,c2,c3;
//Instantiate 4 full 1 bit adders
fulladd fa0(sum[0],c1,a[0],b[0],c_in);
fulladd fa1(sum[1],c2,a[1],b[1],c1);
fulladd fa2(sum[2],c3,,a[2],b[2],c2);
fulladd fa3(sum[3],c_out,a[3],b[3],c3);
endmodule
有人能解释一下我的错误吗？在第67行，c3后面有两个逗号。如果您删除其中一个，它应该可以正常工作
fulladd fa2(sum[2],c3,,a[2],b[2],c2);