Verilog 寄存器和整数比较不起作用
我在SystemVerilog中遇到了一个有趣的问题,其中与寄存器的比较不起作用Verilog 寄存器和整数比较不起作用,verilog,system-verilog,fpga,Verilog,System Verilog,Fpga,我在SystemVerilog中遇到了一个有趣的问题,其中与寄存器的比较不起作用 module VGA_Colours ( input wire clk, reset, // input wire [3:0] swred, swgreen, // input wire [1:0] swblue, output wire hsync, vsync, output wire [3:0] r, g, b
module VGA_Colours
(
input wire clk, reset,
// input wire [3:0] swred, swgreen,
// input wire [1:0] swblue,
output wire hsync, vsync,
output wire [3:0] r, g, b
);
// constant declarations for VGA sync parameters
localparam H_DISPLAY = 640; // horizontal display area
localparam H_L_BORDER = 48; // horizontal left border
localparam H_R_BORDER = 16; // horizontal right border
localparam H_RETRACE = 96; // horizontal retrace
localparam H_MAX = H_DISPLAY + H_L_BORDER + H_R_BORDER + H_RETRACE - 1;
localparam START_H_RETRACE = H_DISPLAY + H_R_BORDER;
localparam END_H_RETRACE = H_DISPLAY + H_R_BORDER + H_RETRACE - 1;
localparam V_DISPLAY = 480; // vertical display area
localparam V_T_BORDER = 10; // vertical top border
localparam V_B_BORDER = 33; // vertical bottom border
localparam V_RETRACE = 2; // vertical retrace
localparam V_MAX = V_DISPLAY + V_T_BORDER + V_B_BORDER + V_RETRACE - 1;
localparam START_V_RETRACE = V_DISPLAY + V_B_BORDER;
localparam END_V_RETRACE = V_DISPLAY + V_B_BORDER + V_RETRACE - 1;
wire video_on, p_tick;
reg [9:0] ii;
reg j;
reg [3:0] red_reg, green_reg, blue_reg;
reg [11:0] rbg;
// mod-2 counter to generate 25 MHz pixel tick
reg pixel_reg = 0;
wire pixel_next;
wire pixel_tick;
always @(posedge clk)
pixel_reg <= pixel_next;
assign pixel_next = ~pixel_reg; // next state is complement of current
assign pixel_tick = (pixel_reg == 0); // assert tick half of the time
// registers to keep track of current pixel location
reg [9:0] h_count_reg, h_count_next, v_count_reg, v_count_next;
// register to keep track of vsync and hsync signal states
reg vsync_reg, hsync_reg;
wire vsync_next, hsync_next;
// infer registers
always @(posedge clk)
if(~reset)
begin
v_count_reg <= 0;
h_count_reg <= 0;
vsync_reg <= 0;
hsync_reg <= 0;
end
else
begin
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
vsync_reg <= vsync_next;
hsync_reg <= hsync_next;
end
// next-state logic of horizontal vertical sync counters
always @*
begin
h_count_next = pixel_tick ?
h_count_reg == H_MAX ? 0 : h_count_reg + 1
: h_count_reg;
v_count_next = pixel_tick && h_count_reg == H_MAX ?
(v_count_reg == V_MAX ? 0 : v_count_reg + 1)
: v_count_reg;
end
// hsync and vsync are active low signals
// hsync signal asserted during horizontal retrace
assign hsync_next = h_count_reg >= START_H_RETRACE
&& h_count_reg <= END_H_RETRACE;
// vsync signal asserted during vertical retrace
assign vsync_next = v_count_reg >= START_V_RETRACE
&& v_count_reg <= END_V_RETRACE;
// video only on when pixels are in both horizontal and vertical display region
assign video_on = (h_count_reg < H_DISPLAY)
&& (v_count_reg < V_DISPLAY);
// output signals
assign hsync = hsync_reg;
assign vsync = vsync_reg;
assign p_tick = pixel_tick;
always @(posedge p_tick) begin
if (~reset) begin
rbg <= 12'b000000000000;
ii <= 9'b0;
end else begin
if (h_count_reg == 0) begin
rbg <= 12'b000000000000;
ii <= 9'b0;
end else if (h_count_reg == ii) begin
ii <= ii + 9'b001010000;
rbg <= rbg + 12'b000010000000;
end
end
end
// output
assign r = (video_on) ? rbg[11:8] : 4'b0;
assign g = (video_on) ? rbg[7:4] : 4'b0;
assign b = (video_on) ? rbg[3:0] : 4'b0;
endmodule
模拟波:
module VGA_Colours_tb ();
logic clk;
reg reset;
wire hsync, vsync;
wire [3:0] r, g, b;
VGA_Colours scr0 (
.clk (clk),
.reset (reset),
.hsync (hsync),
.vsync (vsync),
.r (r),
.b (b),
.g (g)
);
initial begin
clk = 0;
forever #10 clk = ~clk;
end
always @(posedge clk) begin
#20
reset <= 1'b0;
#20
reset <= 1'b1;
#100000
$finish;
end
endmodule
从代码中可以看到,当h_count_reg==到ii时,增加rbg和ii的值。但是,根据模拟波形,它并没有这样做,就好像h_count_reg的值不等于ii,而实际上它等于ii。VGA_colors模块中存在逻辑错误 以下是缩进更加一致的代码:
always @(posedge p_tick) begin
if (~reset) begin
rbg <= 12'b000000000000;
ii <= 9'b0;
end else begin
if (h_count_reg == 0) begin
rbg <= 12'b000000000000;
ii <= 9'b0;
end else if (h_count_reg == ii) begin
rbg <= rbg + 12'b000010000000;
ii <= ii + 9'b001010000;
end
end
end
始终@(posedge p_tick)开始
如果(~reset)开始
rbg您好,我正在尝试使用FPGA板的VGA根据像素位置显示不同的颜色。当我在水平比例上硬编码像素的位置时,我可以看到不同颜色的不同列,这就是我要寻找的结果(类似于旧电视频道脱机时,您可以看到不同颜色的列)。现在,由于我不想硬编码像素位置,我创建了一个变量“I”,每当像素的位置等于“I”的值时,该变量将增加80,屏幕显示黑色,这是初始颜色您看到的问题是用于合成或行为模拟的?不确定您所说的合成或行为是什么意思,user12750353。您好,我已经再次编辑了代码,因为我在调查问题时修改了部分代码。我还包括了我的测试台代码和模拟图