Vhdl 使用计数器运行3到7解码器

我试图运行我的3到7解码器使用输入来自我的计数器，所有的个别代码运行良好，但结构代码放弃了一些错误

这是我柜台的程序

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity counter is  
   port(clk , CLR : in std_logic;
   Q : out std_logic_vector(2 downto 0) );    
end counter;

architecture archi of counter is

    signal tmp: std_logic_vector(2 downto 0);  

    begin      
    process (clk, CLR)   
         begin       

         if (CLR='1') then                  
             tmp <= "000";                       
         elsif (clk'event and clk='1') then  
              tmp <= tmp + 1;                     
          end if;        

     end process;   

     Q <= tmp;

 end archi;

这就是出现的错误：错误
ncvhdl_p:*E，FMLBAD（led_计数，85 | 44）：元素关联87[4.3.3.2]93[4.3.2.2]的形式不良部分。 错误：1，警告：0“

---

注意，符号

led\u计数

未显示在VHDL设计说明中，这是文件名吗

在led_设计中有两个标签L1，它还缺少信号h与信号I匹配的声明（这也告诉您它在其他任何地方都没有使用）

计数器

关联列表（端口映射）与组件声明不匹配。修复这些内容后，代码将进行分析。注意

h

不会在其他任何地方使用

阅读文章，学习如何格式化代码，这太糟糕了

由于缺乏正确的格式和无法理解错误，那些能够回答的人无法提供答案

试试这个：

library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity counter is  
   port(clk , CLR : in std_logic;    
         Q : out std_logic_vector(2 downto 0) ); 
end counter;

architecture archi of counter is

    signal tmp: std_logic_vector(2 downto 0);  

begin  

    process (clk, CLR)   
    begin       

        if (CLR='1') then                
            tmp <= "000";        
        elsif (clk'event and clk='1') then      
            tmp <= std_logic_vector(unsigned(tmp) + 1);             
        end if;        

    end process;   

    Q <= tmp;

end archi;



library IEEE;
use IEEE.std_logic_1164.all;

entity led_inp is
    port (I : in std_logic_vector(2 downto 0) ;
          L : out std_logic_vector(6 downto 0) ) ;
end led_inp ;

architecture led_inp1 of led_inp is 

Begin 

    L(0) <= (not I(0)) and (not I(1)) and (not I(2));
    L(1) <= (not I(0)) and (not I(1)) and I(2);
    L(2) <= (not I(0)) and I(1) and (not I(2));
    L(3) <= (not I(0)) and I(1) and I(2);
    L(4) <= I(0) and (not I(1)) and (not I(2));
    L(5) <= I(0) and (not I(1)) and I(2);
    L(6) <= I(0) and I(1) and (not I(2));

end led_inp1;



 library IEEE;
 use IEEE.std_logic_1164.all;

 entity led_design is 
     port(clock,CLEAR :in std_logic;    
          L :out std_logic_vector(6 downto 0));
 end led_design; 

 architecture led_design1 of led_design is

     component counter   
         port(clk, CLR : in std_logic;     
             Q : out std_logic_vector(2 downto 0) );
     end component ;

     component led_inp 
         port (I : in std_logic_vector(2 downto 0) ;
               L : out std_logic_vector(6 downto 0)) ;
     end component  ;

     signal I:std_logic_vector(2 downto 0);
     signal h:std_logic_vector(2 downto 0);
begin 

L1: counter port map (
      clk=>clock,CLR=>CLEAR, Q => I); -- I(2)=>I(2),I(1)=>I(1),I(0)=>I(0)); 

L2: led_inp port map ( I(2)=>I(2),I(1)=>I(1),I(0)=>I(0),L(0)=>L(0),L(1)=>L(1),L(2)=>L(2),L(3)=>L(3),L(4)=>L(4),L(5)=>L(5),L(6)=>L(6));

L3: counter port map( clk=>clock,CLR=>CLEAR, Q => h);-- I(2)=>h(2),I(1)=>h(1),I(0)=>h(0));
-- ERROR 
--**ncvhdl_p: *E,FMLBAD (led_count,85|44): poorly formed formal part of element association 87[4.3.3.2] 93[4.3.2.2].
--  errors: 1, warnings: 0"**


end led_design1;

IEEE库；
使用IEEE.std_logic_1164.all；
--使用IEEE.std_logic_unsigned.all；
使用ieee.numeric_std.all；
实体计数器为
端口（clk，CLR:标准逻辑中；
Q：输出标准逻辑向量（2到0）；
末端计数器；
计数器的架构是
信号tmp:std_逻辑_向量（2到0）；
开始
进程（clk、CLR）
开始
如果（CLR='1'），则
tmp welcome@Justus，您应该修复代码的格式设置（因此它的格式良好并突出显示），并解释您试图实现的目标：）@AdrieanKhisbe抱歉，我正在尝试使用counter@DavidKoontz对不起，我之前犯的错误是我错误复制的旧错误，请原谅。led_count确实是文件名！！下一次的一些提示@Justus，注意代码的格式。在标记中，您只需要四个前导空格。行间的空格不是必需的。如果您想了解有关标记格式的更多信息，请查看此处：）您可以查看一下吗！！很抱歉，我以前发布的错误是早期错误！！我已更新了此设计中出现的错误，我没有看到任何错误更新“错误ncvhdl_p:*E，FMLBAD（led_计数，85 | 44）：元素关联的形式不良部分87[4.3.3.2]93[4.3.2.2]。错误：1，警告：0“。还是一样。请格式化问题中的代码。谢谢，它成功了！！非常感谢大卫！！我为所有这些恼人的问题感到抱歉。我对stackoverflow和HDL编程是完全陌生的
library IEEE;

use IEEE.std_logic_1164.all;

-- the entity of the whole design block, here i have given the names of the ports as the ones which i have used in my individual components 

entity led_design is  
    port(clock,CLEAR :in std_logic;        
    L :out std_logic_vector(6 downto 0));   
end led_design; 

architecture led_design1 of led_design is 
-- declaring my counter as a component 
   component counter   
   port(clk, CLR : in std_logic;     
   Q : out std_logic_vector(2 downto 0) );
 end component ;

-- declaring my decoder as a component 

component led_inp 
    port (I : in std_logic_vector(2 downto 0) ;
    L : out std_logic_vector(6 downto 0)) ;
end component  ;

signal I:std_logic_vector(2 downto 0);
begin 
    -- The PORT MAPPING BEGINS 

    L1: counter port map(clk=>clock,CLR=>CLEAR,I(2)=>I(2),I(1)=>I(1),I(0)=>I(0)); 

    L2: led_inp port map(I(2)=>I(2),I(1)=>I(1),I(0)=>I(0),L(0)=>L(0),L(1)=>L(1),L(2)=>L(2),L(3)=>L(3),L(4)=>L(4),L(5)=>L(5),L(6)=>L(6));

    L1: counter port 

    map(clk=>clock,CLR=>CLEAR,I(2)=>h(2),I(1)=>h(1),I(0)=>h(0)); 
end led_design1;

library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity counter is  
   port(clk , CLR : in std_logic;    
         Q : out std_logic_vector(2 downto 0) ); 
end counter;

architecture archi of counter is

    signal tmp: std_logic_vector(2 downto 0);  

begin  

    process (clk, CLR)   
    begin       

        if (CLR='1') then                
            tmp <= "000";        
        elsif (clk'event and clk='1') then      
            tmp <= std_logic_vector(unsigned(tmp) + 1);             
        end if;        

    end process;   

    Q <= tmp;

end archi;



library IEEE;
use IEEE.std_logic_1164.all;

entity led_inp is
    port (I : in std_logic_vector(2 downto 0) ;
          L : out std_logic_vector(6 downto 0) ) ;
end led_inp ;

architecture led_inp1 of led_inp is 

Begin 

    L(0) <= (not I(0)) and (not I(1)) and (not I(2));
    L(1) <= (not I(0)) and (not I(1)) and I(2);
    L(2) <= (not I(0)) and I(1) and (not I(2));
    L(3) <= (not I(0)) and I(1) and I(2);
    L(4) <= I(0) and (not I(1)) and (not I(2));
    L(5) <= I(0) and (not I(1)) and I(2);
    L(6) <= I(0) and I(1) and (not I(2));

end led_inp1;



 library IEEE;
 use IEEE.std_logic_1164.all;

 entity led_design is 
     port(clock,CLEAR :in std_logic;    
          L :out std_logic_vector(6 downto 0));
 end led_design; 

 architecture led_design1 of led_design is

     component counter   
         port(clk, CLR : in std_logic;     
             Q : out std_logic_vector(2 downto 0) );
     end component ;

     component led_inp 
         port (I : in std_logic_vector(2 downto 0) ;
               L : out std_logic_vector(6 downto 0)) ;
     end component  ;

     signal I:std_logic_vector(2 downto 0);
     signal h:std_logic_vector(2 downto 0);
begin 

L1: counter port map (
      clk=>clock,CLR=>CLEAR, Q => I); -- I(2)=>I(2),I(1)=>I(1),I(0)=>I(0)); 

L2: led_inp port map ( I(2)=>I(2),I(1)=>I(1),I(0)=>I(0),L(0)=>L(0),L(1)=>L(1),L(2)=>L(2),L(3)=>L(3),L(4)=>L(4),L(5)=>L(5),L(6)=>L(6));

L3: counter port map( clk=>clock,CLR=>CLEAR, Q => h);-- I(2)=>h(2),I(1)=>h(1),I(0)=>h(0));
-- ERROR 
--**ncvhdl_p: *E,FMLBAD (led_count,85|44): poorly formed formal part of element association 87[4.3.3.2] 93[4.3.2.2].
--  errors: 1, warnings: 0"**


end led_design1;