Vhdl JK触发器代码调试

以下是JK触发器的代码：-

entity jkasync is
Port ( j : in std_logic;
       k : in std_logic;
       r : in std_logic;
       clk : in std_logic;
       q : inout std_logic);
 end jkasync;

architecture Behavioral of jkasync is
signal s: std_logic_vector(1 downto 0);
s <= j&k;
begin

  process (j,k,r,clk)
  begin

        if (r='1') then
        q<='0';
        elsif (falling_edge(clk)) then
        case    s is
        when "00" =>q<=q;
        when "01" =>q<='0';
        when "10" =>q<='1';
        when "11" =>q<= not q;
        when others =>q<='0';
        end case;
        end if;
    end process;


  end Behavioral;

实体jkancy是
端口（j:std_逻辑中的；
k：标准逻辑；
r：在标准逻辑中；
clk：标准逻辑中；
q:inout标准逻辑）；
结束jksync；
jksync的行为体系结构是
信号s:std_逻辑_向量（1到0）；
s明白了

新信号在架构体中初始化，但值在流程体中定义

因此，将第21行移到进程内

正确代码：-

   architecture Behavioral of jkasync is
  signal s: std_logic_vector(1 downto 0);

  begin
  s <= j&k;
  process (j,k,r,clk)
  begin

        if (r='1') then
        q<='0';
        elsif (falling_edge(clk)) then
        case    s is
        when "00" =>q<=q;
        when "01" =>q<='0';
        when "10" =>q<='1';
        when "11" =>q<= not q;
        when others =>q<='0';
        end case;
        end if;
    end process;


        end Behavioral;

jkancy的行为架构是
信号s:std_逻辑_向量（1到0）；
开始
在架构开始之前，您不能进行任何信号分配。