VHDL错误std_逻辑类型与整数文字不匹配
我是VHDL新手,在尝试编译代码时遇到以下错误: 错误(10517):vga_控制器上的VHDL类型不匹配错误。vhd(60):std_逻辑类型与整数文本不匹配 错误(10327):vga_控制器上出现VHDL错误。vhd(60):无法确定运算符“-”的定义--找到0个可能的定义 似乎问题在于h_计数,在设置为STD_逻辑之前,我将其设置为整数,如下所示: 错误(10476):vga_控制器上的VHDL错误。vhd(104):标识符“h_计数”的类型与其作为“std_逻辑_向量”类型的用法不一致 因此,我将其更改为STD_逻辑,但它只会给我另一条错误消息VHDL错误std_逻辑类型与整数文字不匹配,vhdl,Vhdl,我是VHDL新手,在尝试编译代码时遇到以下错误: 错误(10517):vga_控制器上的VHDL类型不匹配错误。vhd(60):std_逻辑类型与整数文本不匹配 错误(10327):vga_控制器上出现VHDL错误。vhd(60):无法确定运算符“-”的定义--找到0个可能的定义 似乎问题在于h_计数,在设置为STD_逻辑之前,我将其设置为整数,如下所示: 错误(10476):vga_控制器上的VHDL错误。vhd(104):标识符“h_计数”的类型与其作为“std_逻辑_向量”类型的用法不一致
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY vga_controller IS
GENERIC(
h_pulse : INTEGER := 128; --horiztonal sync pulse width in pixels
h_bp : INTEGER := 88; --horiztonal back porch width in pixels
h_pixels : INTEGER := 800; --horiztonal display width in pixels
h_fp : INTEGER := 40; --horiztonal front porch width in pixels
h_pol : STD_LOGIC := '1'; --horizontal sync pulse polarity (1 = positive, 0 = negative)
v_pulse : INTEGER := 4;
v_bp : INTEGER := 23; --vertical back porch width in rows
v_pixels : INTEGER := 600; --vertical display width in rows
v_fp : INTEGER := 1; --vertical front porch width in rows
v_pol : STD_LOGIC := '1'); --vertical sync pulse polarity (1 = positive, 0 = negative)
PORT(
pixel_clk : IN STD_LOGIC; --pixel clock at frequency of VGA mode being used
reset_n : IN STD_LOGIC; --active low asycnchronous reset
h_sync : OUT STD_LOGIC; --horiztonal sync pulse
v_sync : OUT STD_LOGIC; --vertical sync pulse
disp_ena : OUT STD_LOGIC; --display enable ('1' = display time, '0' = blanking time)
column : OUT STD_LOGIC_VECTOR (10 downto 0); --horizontal pixel coordinate
row : OUT STD_LOGIC_VECTOR (10 downto 0); --vertical pixel coordinate
n_blank : OUT STD_LOGIC; --direct blacking output to DAC
n_sync : OUT STD_LOGIC); --sync-on-green output to DAC
END vga_controller;
ARCHITECTURE behavior OF vga_controller IS
CONSTANT h_period : INTEGER := h_pulse + h_bp + h_pixels + h_fp; --total number of pixel clocks in a row
CONSTANT v_period : INTEGER := v_pulse + v_bp + v_pixels + v_fp; --total number of rows in column
BEGIN
BEGIN
n_blank <= '1'; --no direct blanking
n_sync <= '0'; --no sync on green
PROCESS(pixel_clk, reset_n)
VARIABLE h_count : STD_LOGIC RANGE 0 TO h_period - 1 := 0; --horizontal counter (counts the columns)
VARIABLE v_count : STD_LOGIC RANGE 0 TO v_period - 1 := 0; --vertical counter (counts the rows)
BEGIN
IF(reset_n = '0') THEN --reset asserted
h_count := 0; --reset horizontal counter
v_count := 0; --reset vertical counter
h_sync <= NOT h_pol; --deassert horizontal sync
v_sync <= NOT v_pol; --deassert vertical sync
disp_ena <= '0'; --disable display
column <= "00000000000"; --reset column pixel coordinate
row <= "00000000000"; --reset row pixel coordinate
ELSIF(pixel_clk'EVENT AND pixel_clk = '1') THEN
--counters
IF(h_count < h_period - 1) THEN --horizontal counter (pixels)
h_count := h_count + 1;
ELSE
h_count := 0;
IF(v_count < v_period - 1) THEN --veritcal counter (rows)
v_count := v_count + 1;
ELSE
v_count := 0;
END IF;
END IF;
--horizontal sync signal
IF(h_count < h_pixels + h_fp OR h_count > h_pixels + h_fp + h_pulse) THEN
h_sync <= NOT h_pol; --deassert horiztonal sync pulse
ELSE
h_sync <= h_pol; --assert horiztonal sync pulse
END IF;
--vertical sync signal
IF(v_count < v_pixels + v_fp OR v_count > v_pixels + v_fp + v_pulse) THEN
v_sync <= NOT v_pol; --deassert vertical sync pulse
ELSE
v_sync <= v_pol; --assert vertical sync pulse
END IF;
--set pixel coordinates
IF(h_count < h_pixels) THEN --horiztonal display time
column <= h_count; --set horiztonal pixel coordinate
END IF;
IF(v_count < v_pixels) THEN --vertical display time
row <= v_count; --set vertical pixel coordinate
END IF;
--set display enable output
IF(h_count < h_pixels AND v_count < v_pixels) THEN --display time
disp_ena <= '1'; --enable display
ELSE --blanking time
disp_ena <= '0'; --disable display
END IF;
END IF;
END PROCESS;
END behavior;
ieee库;
使用ieee.std_logic_1164.all;
使用ieee.numeric_std.all;
实体vga_控制器为
一般的(
h_脉冲:整数:=128;--以像素为单位的水平同步脉冲宽度
h_bp:INTEGER:=88;--以像素为单位的水平后廊宽度
h_像素:整数:=800;--以像素为单位的水平显示宽度
h_fp:INTEGER:=40;--水平前廊宽度(以像素为单位)
h_pol:STD_逻辑:='1';--水平同步脉冲极性(1=正,0=负)
v_脉冲:整数:=4;
v_bp:INTEGER:=23;--垂直后廊宽度(以行为单位)
v_像素:整数:=600;--垂直显示行宽度
v_fp:INTEGER:=1;--垂直前廊宽度(以行为单位)
v_pol:STD_逻辑:='1')--垂直同步脉冲极性(1=正极,0=负极)
港口(
像素时钟:在标准逻辑中——使用VGA模式频率的像素时钟
复位n:在标准逻辑中;--低电平主动非同步复位
h_同步:输出标准逻辑;--水平同步脉冲
v_同步:输出标准逻辑;--垂直同步脉冲
disp_ena:OUT STD_LOGIC;--显示启用('1'=显示时间,'0'=消隐时间)
列:OUT STD_LOGIC_VECTOR(10到0);--水平像素坐标
行:输出标准逻辑向量(10到0);--垂直像素坐标
n_blank:OUT STD_LOGIC;--直接黑输出到DAC
n_sync:输出标准逻辑)--将绿色输出同步到DAC
终端控制器;
vga_控制器的架构行为是
恒定h_周期:整数:=h_脉冲+h_bp+h_像素+h_fp--一行中像素时钟的总数
恒定v_周期:整数:=v_脉冲+v_bp+v_像素+v_fp--列中的行总数
开始
开始
n_blank您的问题是您混合了整数和标准逻辑向量类型
例如,在不进行类型转换的情况下,将h\u计数整数指定给列std\u逻辑向量。您的线路:
column <= h_count;
column您提供的错误消息中的行号与代码片段不匹配,并且您有一个重复的架构开始
返回原始设计规范:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY vga_controller IS
GENERIC(
h_pulse : INTEGER := 128; --horiztonal sync pulse width in pixels
h_bp : INTEGER := 88; --horiztonal back porch width in pixels
h_pixels : INTEGER := 800; --horiztonal display width in pixels
h_fp : INTEGER := 40; --horiztonal front porch width in pixels
h_pol : STD_ULOGIC := '1'; --horizontal sync pulse polarity (1 = positive, 0 = negative)
v_pulse : INTEGER := 4;
v_bp : INTEGER := 23; --vertical back porch width in rows
v_pixels : INTEGER := 600; --vertical display width in rows
v_fp : INTEGER := 1; --vertical front porch width in rows
v_pol : STD_ULOGIC := '1' --vertical sync pulse polarity (1 = positive, 0 = negative)
);
PORT(
pixel_clk : IN STD_LOGIC; --pixel clock at frequency of VGA mode being used
reset_n : IN STD_LOGIC; --active low asycnchronous reset
h_sync : OUT STD_LOGIC; --horiztonal sync pulse
v_sync : OUT STD_LOGIC; --vertical sync pulse
disp_ena : OUT STD_LOGIC; --display enable ('1' = display time, '0' = blanking time)
column : OUT STD_LOGIC_VECTOR (10 downto 0); --horizontal pixel coordinate
row : OUT STD_LOGIC_VECTOR (10 downto 0); --vertical pixel coordinate
n_blank : OUT STD_LOGIC; --direct blacking output to DAC
n_sync : OUT STD_LOGIC --sync-on-green output to DAC
);
END vga_controller;
ARCHITECTURE behavior OF vga_controller IS
CONSTANT h_period : INTEGER := h_pulse + h_bp + h_pixels + h_fp; --total number of pixel clocks in a row
CONSTANT v_period : INTEGER := v_pulse + v_bp + v_pixels + v_fp; --total number of rows in column
BEGIN
n_blank <= '1'; --no direct blanking
n_sync <= '0'; --no sync on green
frame_counters:
PROCESS(pixel_clk, reset_n)
VARIABLE h_count : INTEGER RANGE 0 TO h_period - 1 := 0; --horizontal counter (counts the columns)
VARIABLE v_count : INTEGER RANGE 0 TO v_period - 1 := 0; --vertical counter (counts the rows)
BEGIN
IF(reset_n = '0') THEN --reset asserted
h_count := 0; --reset horizontal counter
v_count := 0; --reset vertical counter
h_sync <= NOT h_pol; --deassert horizontal sync
v_sync <= NOT v_pol; --deassert vertical sync
disp_ena <= '0'; --disable display
column <= "00000000000"; --reset column pixel coordinate
row <= "00000000000"; --reset row pixel coordinate
ELSIF(pixel_clk'EVENT AND pixel_clk = '1') THEN
--counters
IF(h_count < h_period - 1) THEN --horizontal counter (pixels)
h_count := h_count + 1;
ELSE
h_count := 0;
IF(v_count < v_period - 1) THEN --veritcal counter (rows)
v_count := v_count + 1;
ELSE
v_count := 0;
END IF;
END IF;
--horizontal sync signal
IF(h_count < h_pixels + h_fp OR h_count > h_pixels + h_fp + h_pulse) THEN
h_sync <= NOT h_pol; --deassert horiztonal sync pulse
ELSE
h_sync <= h_pol; --assert horiztonal sync pulse
END IF;
--vertical sync signal
IF(v_count < v_pixels + v_fp OR v_count > v_pixels + v_fp + v_pulse) THEN
v_sync <= NOT v_pol; --deassert vertical sync pulse
ELSE
v_sync <= v_pol; --assert vertical sync pulse
END IF;
--set pixel coordinates
IF(h_count < h_pixels) THEN --horiztonal display time
column <= std_logic_vector(to_unsigned(h_count,column'LENGTH)); --set horiztonal pixel coordinate
END IF;
IF(v_count < v_pixels) THEN --vertical display time
row <= std_logic_vector(to_unsigned(v_count,row'LENGTH)); --set vertical pixel coordinate
END IF;
--set display enable output
IF(h_count < h_pixels AND v_count < v_pixels) THEN --display time
disp_ena <= '1'; --enable display
ELSE --blanking time
disp_ena <= '0'; --disable display
END IF;
END IF;
END PROCESS;
END behavior;
ieee库;
使用ieee.std_logic_1164.all;
使用ieee.numeric_std.all;
实体vga_控制器为
一般的(
h_脉冲:整数:=128;--以像素为单位的水平同步脉冲宽度
h_bp:INTEGER:=88;--以像素为单位的水平后廊宽度
h_像素:整数:=800;--以像素为单位的水平显示宽度
h_fp:INTEGER:=40;--水平前廊宽度(以像素为单位)
h_pol:STD_ULOGIC:=“1”;--水平同步脉冲极性(1=正,0=负)
v_脉冲:整数:=4;
v_bp:INTEGER:=23;--垂直后廊宽度(以行为单位)
v_像素:整数:=600;--垂直显示行宽度
v_fp:INTEGER:=1;--垂直前廊宽度(以行为单位)
v_pol:STD_ULOGIC:=“1”-垂直同步脉冲极性(1=正,0=负)
);
港口(
像素时钟:在标准逻辑中——使用VGA模式频率的像素时钟
复位n:在标准逻辑中;--低电平主动非同步复位
h_同步:输出标准逻辑;--水平同步脉冲
v_同步:输出标准逻辑;--垂直同步脉冲
disp_ena:OUT STD_LOGIC;--显示启用('1'=显示时间,'0'=消隐时间)
列:OUT STD_LOGIC_VECTOR(10到0);--水平像素坐标
行:输出标准逻辑向量(10到0);--垂直像素坐标
n_blank:OUT STD_LOGIC;--直接黑输出到DAC
n_sync:OUT STD_逻辑——绿色输出同步到DAC
);
终端控制器;
vga_控制器的架构行为是
恒定h_周期:整数:=h_脉冲+h_bp+h_像素+h_fp--一行中像素时钟的总数
恒定v_周期:整数:=v_脉冲+v_bp+v_像素+v_fp--列中的行总数
开始
n\u blank如果您希望位向量表示一个数字,请使用ieee.numeric\u std
库,然后使用无符号
和/或有符号
类型。和/或使用integer
s
h_count <= to_integer(unsigned(column));
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY vga_controller IS
GENERIC(
h_pulse : INTEGER := 128; --horiztonal sync pulse width in pixels
h_bp : INTEGER := 88; --horiztonal back porch width in pixels
h_pixels : INTEGER := 800; --horiztonal display width in pixels
h_fp : INTEGER := 40; --horiztonal front porch width in pixels
h_pol : STD_ULOGIC := '1'; --horizontal sync pulse polarity (1 = positive, 0 = negative)
v_pulse : INTEGER := 4;
v_bp : INTEGER := 23; --vertical back porch width in rows
v_pixels : INTEGER := 600; --vertical display width in rows
v_fp : INTEGER := 1; --vertical front porch width in rows
v_pol : STD_ULOGIC := '1' --vertical sync pulse polarity (1 = positive, 0 = negative)
);
PORT(
pixel_clk : IN STD_LOGIC; --pixel clock at frequency of VGA mode being used
reset_n : IN STD_LOGIC; --active low asycnchronous reset
h_sync : OUT STD_LOGIC; --horiztonal sync pulse
v_sync : OUT STD_LOGIC; --vertical sync pulse
disp_ena : OUT STD_LOGIC; --display enable ('1' = display time, '0' = blanking time)
column : OUT STD_LOGIC_VECTOR (10 downto 0); --horizontal pixel coordinate
row : OUT STD_LOGIC_VECTOR (10 downto 0); --vertical pixel coordinate
n_blank : OUT STD_LOGIC; --direct blacking output to DAC
n_sync : OUT STD_LOGIC --sync-on-green output to DAC
);
END vga_controller;
ARCHITECTURE behavior OF vga_controller IS
CONSTANT h_period : INTEGER := h_pulse + h_bp + h_pixels + h_fp; --total number of pixel clocks in a row
CONSTANT v_period : INTEGER := v_pulse + v_bp + v_pixels + v_fp; --total number of rows in column
BEGIN
n_blank <= '1'; --no direct blanking
n_sync <= '0'; --no sync on green
frame_counters:
PROCESS(pixel_clk, reset_n)
VARIABLE h_count : INTEGER RANGE 0 TO h_period - 1 := 0; --horizontal counter (counts the columns)
VARIABLE v_count : INTEGER RANGE 0 TO v_period - 1 := 0; --vertical counter (counts the rows)
BEGIN
IF(reset_n = '0') THEN --reset asserted
h_count := 0; --reset horizontal counter
v_count := 0; --reset vertical counter
h_sync <= NOT h_pol; --deassert horizontal sync
v_sync <= NOT v_pol; --deassert vertical sync
disp_ena <= '0'; --disable display
column <= "00000000000"; --reset column pixel coordinate
row <= "00000000000"; --reset row pixel coordinate
ELSIF(pixel_clk'EVENT AND pixel_clk = '1') THEN
--counters
IF(h_count < h_period - 1) THEN --horizontal counter (pixels)
h_count := h_count + 1;
ELSE
h_count := 0;
IF(v_count < v_period - 1) THEN --veritcal counter (rows)
v_count := v_count + 1;
ELSE
v_count := 0;
END IF;
END IF;
--horizontal sync signal
IF(h_count < h_pixels + h_fp OR h_count > h_pixels + h_fp + h_pulse) THEN
h_sync <= NOT h_pol; --deassert horiztonal sync pulse
ELSE
h_sync <= h_pol; --assert horiztonal sync pulse
END IF;
--vertical sync signal
IF(v_count < v_pixels + v_fp OR v_count > v_pixels + v_fp + v_pulse) THEN
v_sync <= NOT v_pol; --deassert vertical sync pulse
ELSE
v_sync <= v_pol; --assert vertical sync pulse
END IF;
--set pixel coordinates
IF(h_count < h_pixels) THEN --horiztonal display time
column <= std_logic_vector(to_unsigned(h_count,column'LENGTH)); --set horiztonal pixel coordinate
END IF;
IF(v_count < v_pixels) THEN --vertical display time
row <= std_logic_vector(to_unsigned(v_count,row'LENGTH)); --set vertical pixel coordinate
END IF;
--set display enable output
IF(h_count < h_pixels AND v_count < v_pixels) THEN --display time
disp_ena <= '1'; --enable display
ELSE --blanking time
disp_ena <= '0'; --disable display
END IF;
END IF;
END PROCESS;
END behavior;
--set pixel coordinates
IF(h_count < h_pixels) THEN --horiztonal display time
column <= std_logic_vector(to_unsigned(h_count,column'LENGTH)); --set horiztonal pixel coordinate
END IF;
IF(v_count < v_pixels) THEN --vertical display time
row <= std_logic_vector(to_unsigned(v_count,row'LENGTH)); --set vertical pixel coordinate
END IF;