VHDL移位寄存器未向右旋转
有人能帮我弄清楚为什么我的移位寄存器不能正确旋转吗。我知道这不是开关输入,因为我用sw15切换了sw14,它仍然向左旋转,但不是向右旋转。我认为这是在实际的编码,但我不知道什么VHDL移位寄存器未向右旋转,vhdl,shift,Vhdl,Shift,有人能帮我弄清楚为什么我的移位寄存器不能正确旋转吗。我知道这不是开关输入,因为我用sw15切换了sw14,它仍然向左旋转,但不是向右旋转。我认为这是在实际的编码,但我不知道什么 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity question2 is Port ( led: buffer std_logic_vector (9 downto 0); clk: in s
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity question2 is
Port (
led: buffer std_logic_vector (9 downto 0);
clk: in std_logic;
btnU: in std_logic;
btnD: in std_logic;
btnC: in std_logic;
sw: in std_logic_vector (15 downto 14)--------rotate prob. is not in switches
);
end question2;
architecture Behavioral of question2 is
constant active: std_logic :='1';
signal DataIn: std_logic_vector (9 downto 0):= "0000000001";
signal Load: std_logic := btnD;
signal Reset: std_logic := btnC;
signal Left: std_logic:= sw(15);
signal Right: std_logic:= sw(14);
signal DataOut: std_logic_vector (9 downto 0);
signal Clear: std_logic:= btnU;
signal speed_enable: std_logic;
begin
led<= DataOut;
SpeedControl: process (clk, Reset)
variable counter: integer range 0 to 10000000;
begin
speed_enable<=not active;
if Reset = Active then
counter:= 0;
elsif (rising_edge (clk)) then
counter := counter + 1;
if (counter=10000000) then
speed_enable<= Active;
counter:=0;
end if;
end if;
end process;
shiftregister: process(clk, clear)
begin
if rising_edge (clk) then
if clear= active or reset=active then
DataOut <= (others => '0');
elsif load = active then
DataOut <= DataIn ;
elsif Left = active and Right = not active then
if speed_enable = active then
DataOut <= DataOut(8 downto 0) & DataOut(9) ;
elsif Right = active and left = not active then
if speed_enable = active then
DataOut <= DataOut(0) & DataOut (9 downto 1) ;
else
dataout <= "0000000000";
end if;
end if;
end if;
end if;
end process;
end Behavioral;
你还没有解决我在上一个问题上提到的所有问题。默认分配不是默认连接;当软件输入改变时,左右信号不会改变 您应该将内部控制信号连接到led正下方的输入