多输出块Ram的VHDL综合 如果上升沿(时钟100Mhz),则 如果w_ram='1',则 对于0到6循环中的X 对于0到6循环中的Y DataO(X)(Y)(0)
我猜您希望Xilinx合成工具推断多个非对称块RAM。Xilinx有推断一个RAM的示例代码,可以在 写入端口宽8位,深256位,读取端口宽32位,深64位。以下是上述链接中的代码:多输出块Ram的VHDL综合 如果上升沿(时钟100Mhz),则 如果w_ram='1',则 对于0到6循环中的X 对于0到6循环中的Y DataO(X)(Y)(0),vhdl,fpga,Vhdl,Fpga,我猜您希望Xilinx合成工具推断多个非对称块RAM。Xilinx有推断一个RAM的示例代码,可以在 写入端口宽8位,深256位,读取端口宽32位,深64位。以下是上述链接中的代码: if rising_edge(CLK_100Mhz) then if w_ram = '1' then for X in 0 to 6 loop for Y in 0 to 6 loop DataO(X)(Y)(0) <= Memory(X)(Y)(Add
if rising_edge(CLK_100Mhz) then
if w_ram = '1' then
for X in 0 to 6 loop
for Y in 0 to 6 loop
DataO(X)(Y)(0) <= Memory(X)(Y)(Address);
DataO(X)(Y)(1) <= Memory(X)(Y)(Address+1);
DataO(X)(Y)(2) <= Memory(X)(Y)(Address+2);
DataO(X)(Y)(3) <= Memory(X)(Y)(Address+3);
Memory(X)(Y)(Address) <= DataI(X)(Y)(0);
end loop;
end loop;
w_ram <= '0';
end if;
end if;
——非对称端口RAM
--端口A仅为256x8位写
--端口B为64x32位只读
--
--下载:ftp://ftp.xilinx.com/pub/documentation/misc/xstug_examples.zip
--文件:HDL_编码_技术/rams/asymetric_ram_1a.vhd
--
图书馆ieee;
使用ieee.std_logic_1164.all;
使用ieee.std_logic_unsigned.all;
使用ieee.std_logic_arith.all;
实体非对称_ram_1a是
一般的(
宽度A:整数:=8;
SIZEA:整数:=256;
ADDRWIDTHA:整数:=8;
宽度b:整数:=32;
SIZEB:整数:=64;
ADDRWIDTHB:整数:=6
);
港口(
clkA:标准逻辑;
clkB:标准逻辑中;
weA:标准逻辑;
enA:标准逻辑;
enB:标准逻辑;
addrA:在标准逻辑向量中(ADDRWIDTHA-1向下至0);
addrB:在标准逻辑向量中(ADDRWIDTHB-1降到0);
直径:标准逻辑向量(宽度A-1至0);
doB:out标准逻辑向量(宽度B-1向下至0)
);
端部非对称闸板1a;
非对称_ram_1a的行为体系结构是
函数max(L,R:INTEGER)返回的整数为
开始
如果L>R,那么
返回L;
其他的
返回R;
如果结束;
结束;
函数min(L,R:INTEGER)返回的整数为
开始
如果L(其他=>“0”);
信号读取B:std_逻辑_向量(宽度B-1向下至0):=(其他=>'0');
信号regB:std_逻辑_向量(宽度b-1向下至0):=(其他=>'0');
开始
过程(clkA)
开始
如果上升沿(clkA),则
如果enA='1',则
如果weA='1',则
ram(conv_integer(addrA))可以重写代码,这样它只需要一个ram。根据大小,它仍然可能需要多个区块。您可以为地址、数据I、数据O和内存添加使用的数据类型吗?您访问的是连续地址的内存,因此一条内存线将被拆分为4个字。写入内存可以通过使用字节启用来完成。这种类型的东西可以工作,但取决于数据的宽度,在一个时钟周期内访问196个内存位置可能需要大量块。
-- Asymmetric port RAM
-- Port A is 256x8-bit write-only
-- Port B is 64x32-bit read-only
--
-- Download: ftp://ftp.xilinx.com/pub/documentation/misc/xstug_examples.zip
-- File: HDL_Coding_Techniques/rams/asymmetric_ram_1a.vhd
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity asymmetric_ram_1a is
generic (
WIDTHA : integer := 8;
SIZEA : integer := 256;
ADDRWIDTHA : integer := 8;
WIDTHB : integer := 32;
SIZEB : integer := 64;
ADDRWIDTHB : integer := 6
);
port (
clkA : in std_logic;
clkB : in std_logic;
weA : in std_logic;
enA : in std_logic;
enB : in std_logic;
addrA : in std_logic_vector(ADDRWIDTHA-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTHB-1 downto 0);
diA : in std_logic_vector(WIDTHA-1 downto 0);
doB : out std_logic_vector(WIDTHB-1 downto 0)
);
end asymmetric_ram_1a;
architecture behavioral of asymmetric_ram_1a is
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant minWIDTH : integer := min(WIDTHA,WIDTHB);
constant maxWIDTH : integer := max(WIDTHA,WIDTHB);
constant maxSIZE : integer := max(SIZEA,SIZEB);
constant RATIO : integer := maxWIDTH / minWIDTH;
type ramType is array (0 to maxSIZE-1) of std_logic_vector(minWIDTH-1 downto 0);
signal ram : ramType := (others => (others => '0'));
signal readB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0');
signal regB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
ram(conv_integer(addrA)) <= diA;
end if;
end if;
end if;
end process;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
readB(minWIDTH-1 downto 0)
<= ram(conv_integer(addrB&conv_std_logic_vector(0,2)));
readB(2*minWIDTH-1 downto minWIDTH)
<= ram(conv_integer(addrB&conv_std_logic_vector(1,2)));
readB(3*minWIDTH-1 downto 2*minWIDTH)
<= ram(conv_integer(addrB&conv_std_logic_vector(2,2)));
readB(4*minWIDTH-1 downto 3*minWIDTH)
<= ram(conv_integer(addrB&conv_std_logic_vector(3,2)));
end if;
regB <= readB;
end if;
end process;
doB <= regB;
end behavioral;
Synthesizing (advanced) Unit <asymmetric_ram_1a>.
INFO:Xst:3226 - The RAM <Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <readB> <regB>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 256-word x 8-bit | |
| mode | write-first | |
| clkA | connected to signal <clkA> | rise |
| weA | connected to signal <weA_0> | high |
| addrA | connected to signal <addrA> | |
| diA | connected to signal <diA> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
| Port B |
| aspect ratio | 64-word x 32-bit | |
| mode | write-first | |
| clkB | connected to signal <clkB> | rise |
| enB | connected to signal <enB> | high |
| addrB | connected to signal <addrB> | |
| doB | connected to signal <doB> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
Unit <asymmetric_ram_1a> synthesized (advanced).
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# RAMs : 1
256x8:64x32-bit dual-port block RAM : 1