通过ISE用vhdl代码模拟函数
我最近开始学习VHDL。我写了一段VHDL代码来确定算术 声明,但它不起作用。事实上,当我模拟它时,输出并不 更改后,它将保持为0.0。我不知道我的错误在哪里。我需要用电话吗 外部时钟?当我这样做时,它不会改变:-通过ISE用vhdl代码模拟函数,vhdl,Vhdl,我最近开始学习VHDL。我写了一段VHDL代码来确定算术 声明,但它不起作用。事实上,当我模拟它时,输出并不 更改后,它将保持为0.0。我不知道我的错误在哪里。我需要用电话吗 外部时钟?当我这样做时,它不会改变:- library IEEE; use IEEE.STD_LOGIC_1164.ALL; package mypack is type real_vector is array (integer range <>) of real; end mypack; lib
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package mypack is
type real_vector is array (integer range <>) of real;
end mypack;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.mypack.all;
entity convolution is port (
x:in real_vector(0 to 3);
y:in real_vector(0 to 1);
f:out real_vector (0 to 4)
);
end convolution;
architecture Behavioral of convolution is
--signal temp : real_vector (0 to 4):= (others => 0.0);
--signal enable : std_logic :='0';
begin
process (x,y)
variable sum :real;
begin
for n in f'range loop
enable <= '0';
for k in y'range loop
sum:=sum + x(k)*y(n-k);
end loop;
-- temp(n) <= sum;
f(n) <= sum ;
sum:=0.0;
end loop;
enable <= '1';
--if (enable'event and enable='1') then
-- f <= temp;
--end if;
end process;
end Behavioral;
我可以在您的代码示例中看到一些东西: 你使用真正的类型。您应该避免它们,因为它们通常不可合成,只能在模拟中工作。另一种选择可能是使用。 你可以使用变量。只要你不知道自己在做什么,就应该尽量避免使用变量,因为变量的行为与正常信号不同。变量在进程结束时立即分配其值,而信号值在进程结束时分配。因此,变量通常仅用于简化更复杂的语句,例如C中的define语句。 您应该使您的设计同步/计时,并使用寄存器。每个时钟周期进行一次特定操作。
我认为主循环末尾的语句sum:=0.0覆盖了赋值中sum的值fnVHDL不是一种编程语言,它是一种硬件描述语言 因此,重要的是使用std_逻辑_向量、无符号和硬件固有的其他原语,以获得可靠的结果并尽可能优化最终设计 您没有看到输出的变化,因为整个for循环在流程的一次迭代中完全执行。最终结果将只是for循环的最后一个状态,在本例中,它是sum:=0.0;。为了解决这一问题,强烈建议您在设计中使用外部时钟,该时钟是流程灵敏度列表的一部分。这将允许您内在地将流程用作for循环,这将完全消除显式for循环的需要 几天前,EE stack exchange站点上出现了一个非常类似的问题,我写了一个非常全面的答案,解释了如何以这种方式将进程用作for循环 这是我对另一个问题回答的链接。 我已经检查了你的代码,把它修好了一点,还加了一个时钟!。我没有对它进行模拟,所以它可能不会100%按时间执行,但这是一个示例,以了解我使用流程作为for循环的意思,并让您走上正确的轨道 给你
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- unsigned types are part of the numeric_std package. They are like std_logic types, but have native support for +,-,*, etc.
package mypack is
type x_vector is array(0 to 3) of unsigned(0 to 31);
type y_vector is array(0 to 1) of unsigned(0 to 31);
type f_vector is array(0 to 4) of unsigned(0 to 31);
end mypack;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.mypack.all;
entity convolution is
port (
clk : in std_logic;
rst : in std_logic;
x:in x_vector;
y:in y_vector;
f:out f_vector
);
end convolution;
architecture Behavioral of convolution is
signal enable : std_logic;
-- These are your for-loop count variables
signal n_count : unsigned(0 to 4);
signal k_count : unsigned(0 to 1);
-- sum variable (you might want to look into making this 64 bits long, so the answer doesn't overflow)
signal sum : unsigned (0 to 31);
begin
-- process only executes when clock or reset changes
convolve : process (clk,rst)
begin
if (rst = '1') then
-- this is where you set your variables to 0;
n_count <= (others => '0');
k_count <= (others => '0');
sum <= (others => '0');
enable <= '0';
-- nice way of setting all values in f array to zero (nest "others =>" for as many dimensions as you need)
f <= (others => (others => '0'));
elsif (rising_edge(clk)) then
-- if your n counter hits its max value ('high), reset the counter
if (n_count = n_count'high) then
n_count <= (others => '0');
-- Add whatever you want to do when n hits it's max here...
-- This is what is executed while n is counting up.
else
-- if your k counter hits its max value ('high), reset the counter
if (k_count = k_count'high) then
k_count <= (others => '0');
-- Add whatever you want it to do when k hits it's max here...
-- This is what is executed while k is counting up (with n)
else
-- This is where the actual convolution takes place.
-- The counters are converted to integers in order to be used as array references
sum <= sum + sum + (x(to_integer(k_count))*y(to_integer(n_count-k_count)));
-- Increment k!
k_count <= k_count + "1";
end if;
-- Increment n!
n_count <= n_count + "1";
-- I'm not hugely sure what you want to do with the enable, but this is where
-- it was in the other code.
enable <= '0';
-- drive F with sum value
f(to_integer(n_count)) <= sum;
-- clear sum for next round.
sum <= (others => '0');
end if;
-- enable again.
enable <= '1';
end if;
end process;
end Behavioral;
你如何模拟?如果您有一个测试台也发布了它,否则很难说出模拟中错误行为的原因。如果您在内部循环中放置了assert或report语句,它是否会像您预期的那样报告变量的预期值?