错误(10500):实验室06.vhd(54)文本附近的VHDL语法错误;“shifta”;;
错误(10500):lab_06的VHDL语法错误。文本“shifta”附近的vhd(54)错误(10500):实验室06.vhd(54)文本附近的VHDL语法错误;“shifta”;;,vhdl,Vhdl,错误(10500):lab_06的VHDL语法错误。文本“shifta”附近的vhd(54) 在我看来,您似乎试图在体系结构行为之外实例化lab\u 06。您是否编写了结束架构行为,我想问题就在你面前 如果您没有提供导致错误的代码的任何信息,有人应该如何帮助您?请将您的代码粘贴到问题中,而不是共享图像。我的水晶球告诉我错误在第42行。@mfro好的,有错误的行实际上是在他提供的小信息中指定的;) Info: ********************************************
在我看来,您似乎试图在体系结构
行为之外实例化lab\u 06
。您是否编写了结束架构行为代码>,我想问题就在你面前 如果您没有提供导致错误的代码的任何信息,有人应该如何帮助您?请将您的代码粘贴到问题中,而不是共享图像。我的水晶球告诉我错误在第42行。@mfro好的,有错误的行实际上是在他提供的小信息中指定的;)
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Mon Nov 13 18:53:13 2017
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lab_06 -c lab_06
Warning (20028): Parallel compilation is not licensed and has been disabled
Error (10500): VHDL syntax error at lab_06.vhd(30) near text "ktj"; expecting "component"
Error (10500): VHDL syntax error at lab_06.vhd(54) near text "shifta"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"
Info (12021): Found 0 design units, including 0 entities, in source file lab_06.vhd
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 1 warning
Error: Peak virtual memory: 485 megabytes
Error: Processing ended: Mon Nov 13 18:53:14 2017
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus II Full Compilation was unsuccessful. 4 errors, 1 warning