如何在VHDL中实现可变背景色的VGA控制器

我是一个VHDL初学者。为了好玩，我正在尝试用Basys 2 Spartan-3E FPGA培训板实现

640x480@60Hz

VGA控制器。我的目标是使背景颜色不同于黑色，并将两个矩形与背景颜色不同。然而，我得到的结果如下：

有什么问题吗

VHDL代码的相关部分如下所示：

draw: process(clk25,RST,hPos,vPos,videoOn)
begin
    if(RST = '1') then
        RGB <= "00000000";
    elsif(clk25'event and clk25 ='1') then

        if(videoOn <= '1') then
            if((hPos>=10 and hPos <=60) AND (vPos>=10 and vPos <=60) )then
                RGB <= "11111111";

            elsif((hPos>=70 and hPos <= 120) AND (vPos>=10 and vPos <=60 ) )then
                RGB <= "11111110";
            else
                RGB <= "00000011";  
            end if;
        else
            RGB <= "00000000";
        end if;
    end if;
end process;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity vga_driver is
    Port ( CLK   : in  STD_LOGIC;
           RST   : in  STD_LOGIC;
           HSYNC : out  STD_LOGIC;
           VSYNC : out  STD_LOGIC;
           RGB   : out  STD_LOGIC_VECTOR (7 downto 0));
end vga_driver;

architecture Behavioral of vga_driver is

signal clk25 : std_logic := '0';

constant HD  : integer := 639;  -- Horizontal Display
constant HFP : integer := 16;   -- Right border (front)
constant HSP : integer := 96;     -- Sync pulse (retrace)
constant HBP : integer := 48;   -- Left border (back    porch)

constant VD  : integer := 479;  -- Horizontal Display
constant VFP : integer := 10;   -- Right border (front)
constant VSP : integer := 2;      -- Sync pulse (retrace)
constant VBP : integer := 33;   -- Left border (back    porch)

signal hPos: integer := 0;
signal vPos: integer := 0;

signal videoOn: std_logic := '0';
signal frameCounter: std_logic_vector(15 downto 0);


begin

clk_div: process(CLK)
begin
    if(CLK'event and CLK = '1')then
        clk25 <= not clk25;
    end if ;
end process;

Horizontal_pos_counter:process(clk25,RST)
begin
    if(RST = '1') then 
        hPos <= 0;
    elsif(clk25 'event and clk25 = '1')then
        if(hPos = HD + HFP + HSP + HBP) then
            hPos <= 0; 
        else
            hPos <= hPos +1;
        end if;
    end if ;
end process;


Vertical_pos_counter:process(clk25,RST,hPos)
begin
    if(RST = '1') then 
        vPos <= 0;
    elsif(clk25 'event and clk25 = '1')then
        if(hPos = (HD + HFP + HSP + HBP))then
            if(vPos = (VD + VFP + VSP + VBP)) then
                vPos <= 0; 
                if(frameCounter < "1111111111111111") then
                    frameCounter <= frameCounter+1;
                else
                    frameCounter <= (others => '0') ;
                end if;
            else
                vPos <= vPos +1;

            end if;
        end if;
    end if ;
end process;

Horizontal_Synchronisation:process(clk25,RST,hPos)
begin
    if(RST = '1') then
        HSYNC <= '0';
    elsif(clk25'event and clk25 = '1') then
        if((hPos <= (HD + HFP)) OR (hPos > (HD + HFP + HSP)))then
            HSYNC <= '1';
        else
            HSYNC <= '0';
        end if;
    end if;
end process;

Vertical_Synchronisation:process(clk25,RST,hPos)
begin
    if(RST = '1') then
        VSYNC <= '0';
    elsif(clk25'event and clk25 = '1') then
        if((vPos <= (VD + VFP)) OR (vPos > (VD + VFP + VSP))) then
            VSYNC <= '1';
        else
            VSYNC <= '0';
        end if;
    end if;

end process;

video_on: process(clk25,hPos,vPos,RST)
begin
    if(RST = '1') then
        videoOn <= '0';
    elsif(clk25'event and clk25 ='1') then
        if(hPos <= HD and vPos <= VD) then
            videoOn <= '1';
        else
            videoOn <= '0';
        end if;
    end if;

end process;

draw: process(clk25,RST,hPos,vPos,videoOn)
begin
    if(RST = '1') then
        RGB <= "00000000";
    elsif(clk25'event and clk25 ='1') then

        if(videoOn <= '1') then
            if((hPos>=10 and hPos <=60) AND (vPos>=10 and vPos <=60) )then
                RGB <= "11111111";
            elsif((hPos>=70 and hPos <= 120) AND (vPos>=10 and vPos <=60 ) )then
                RGB <= "11111110";
            else
                RGB <= "00000011";  
            end if;
        else
            RGB <= "00000000";
        end if;

    end if;
end process;

end Behavioral;

draw：进程（clk25、RST、hPos、vPos、videoOn）
开始
如果（RST='1'），则
RGB有什么问题？是一个非特定的问题陈述。你是在问这两个矩形区域明显的向右移和边缘参差不齐，还是颜色相同（背景也是黑色的）？前者取决于监视器界面和视频计时，后者取决于将RGB值映射到监视器的颜色。这些似乎是关于显示器连接的电子问题，如果常数正确，则与VHDL描述无关。仔细检查（）表明，rgb在消隐期间从未有值“00000000”（videoOn='0'）。这可能会影响模拟监视器的颜色值箝位。目前还不清楚这是否会影响水平同步位置检测。实际上，在绘制过程中正确设置空白颜色可能是值得的<代码>如果（用于合成或模拟中的二进制的videoOn）图像问题无法复制，因为它是模拟效果造成的。此问题属于on，应该显示监视器连接电路。我在EE堆栈交换中问了此问题。感谢您的评论。